1.4 Limitations

You should not use the processor technology or the supporting deliverables as an indicator of what is received under a full license of the ARM Cortex®-M3 processor.

Example system

Although the system that forms the basis for the design is built from components intended for an ASIC implementation, you are required to consider various conditions when planning to migrate from the example system here to a fully optimized ASIC implementation.

The subsystem provides some support for fine-grained power management, but does not implement any actual power control features. Typically, an ASIC would implement several different clock and power domains aimed at providing good performance without having an undue impact on standby power drain. Some critical guarantees are required for the timing of power rails and control signals, particularly in devices that implement embedded flash memory.

Obfuscated RTL
The obfuscated RTL view gives acceptable results when implemented in the FPGA, but does not provide a good reference for place-and-route prototyping.
There are no standard cell libraries included with Cortex-M3 DesignStart™ Eval.
Peripherals
The peripheral set that is provided for the example FPGA system is limited compared with the full set, which may be required for a small ASIC.
Integration tests
The integration tests included with Cortex-M3 DesignStart Eval can be used as a starting point for a full test suite, but they are not exhaustive and will need to be extended as part of the work to design a full ASIC.
ROM table
The CoreSight™ ROM table is part of the obfuscated CORTEXM3INTEGRATIONDS level, and Cycle Model. This has a fixed device identifier, which indicates that this is an example system supporting the Cortex-M3 processor from ARM. In a production device, the identification registers indicate the company that makes the device, and their own part number.
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