|Non-Confidential||PDF version||ARM 100894_0000_00_en|
|Home > Introduction > Limitations|
You should not use the processor technology or the supporting deliverables as an indicator of what is received under a full license of the ARM Cortex®-M3 processor.
Although the system that forms the basis for the design is built from components intended for an ASIC implementation, you are required to consider various conditions when planning to migrate from the example system here to a fully optimized ASIC implementation.
The subsystem provides some support for fine-grained power management, but does not implement any actual power control features. Typically, an ASIC would implement several different clock and power domains aimed at providing good performance without having an undue impact on standby power drain. Some critical guarantees are required for the timing of power rails and control signals, particularly in devices that implement embedded flash memory.
CORTEXM3INTEGRATIONDSlevel, and Cycle Model. This has a fixed device identifier, which indicates that this is an example system supporting the Cortex-M3 processor from ARM. In a production device, the identification registers indicate the company that makes the device, and their own part number.