6.4 Compiling the RTL

After the simulation environment is configured, with the appropriate licenses available, you can compile the Verilog RTL in the execution_tb directory.

To clean the previous RTL compile, execute the following:

make clean

To compile the RTL, execute the following:

make compile

Only the following configuration options are supported for compiling the RTL:

  • SIMULATOR.
  • DSM.
  • SIM_64BIT.
  • SIM_VCD.
  • FSDB.

For example, to compile the RTL with the processor Cycle Model using the 64-bit Synopsys VCS, execute the following:

make compile SIMULATOR=vcs SIM_64BIT=yes DSM=yes

If the compilation is successful, then the following message is displayed:

>> Testbench compile with vcs and DSM=yes  completed successfully, log in vcs_compile.log

If the compilation fails, then the following is displayed:

 >> ERROR: Testbench compile failed, check vcs_compile.log

The compile log is written to <sim>_compile.log.

Note:

When you compile with DSM=yes, you might observe that the CORTEXM3INTEGRATIONDS_dsm module is reported as uncompiled towards the end of the process. If so, it is compiled at the end (all within the same make compile sequence).
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