5.1 Testbench overview

The testbench in Cortex®-M3 DesignStart™ Eval includes the following:

Table 5-1 Testbench contents

Contents Description
DUT of tb_fpga_shield FPGA top-level module
Reset generator This includes:
  • Powerup reset.
  • Debug reset.
  • FPGA SCC master interface reset.
  • FPGA configuration SPI master interface reset.
Clock generator This includes:
  • System clock at 25MHz.
  • Audio master clock at 12MHz.
  • Audio interface bit clock at 12MHz.
Loop back connection For UARTs and audio I2S testing. This includes:
  • MCU UART (UART0) self-loops back.
  • Console UART (UART1) self-loops back.
  • UART2 connects to UART3 in a crossover arrangement.
  • UART4 self-loops back.
  • Audio I2S self-loops back.
Serial debug driver

Drives the Serial Wire Debug pins based on the content on CXDT.bin in the execution_tb directory generated by the test compilation process.

It is only active when running the cxdt test to demonstrate Serial Wire Debug functionality.

UART text message capture module See 5.2 UART text message capture module.
FPGA configuration SPI master interface driver Writes a set of test vectors after reset to SRAM1 to demonstrate the connectivity from the baseboard Motherboard Configuration Controller (MCC).
Behavioral models See 5.3 Behavioral models.
Arduino shield testbench component

This consists of a behavioral model of:

  • The ARM Arduino shield adapter board.
  • Two Arduino shields connected to the board.

The loop back connection for UART2, 3, and 4 is done in this testbench component.

Pullup and pulldown of various pins The tie-offs are appropriate for normal FPGA operation.
Test code memory initialization See 5.4 Test code memory initialization.
Non-ConfidentialPDF file icon PDF versionARM 100894_0000_00_en
Copyright © 2017 ARM Limited or its affiliates. All rights reserved.