3.4 FPGA peripherals and Arduino shield support

Cortex®-M3 DesignStart™ Eval uses an example system integration to show how a fully functioning system can be built up. This system is built around the ARM Versatile Express Cortex-M Prototyping System (V2M-MPS2+), which provides several peripherals and connectors.

All the FPGA peripherals are connected to one of the AHB master expansion ports.

In addition to the memories integrated in the IoT subsystem in Cortex-M3 DesignStart Eval (and implemented using FPGA block RAM), the on-board ZBT SSRAM, and PSRAM devices are connected to the processor.

The following table lists the included peripherals:

Table 3-2 Included peripherals

Location Supported peripherals
Integrated in subsystem The supported peripherals internal to the example system include:
  • Dual APB timer.
Example system The closely coupled peripherals in the example system include:
  • Dual timer.
  • UART.
  • Real Time Clock (RTC).
  • Watchdog.
  • True Random Number Generator (TRNG).
MPS2+ base board The supported peripherals include:
  • UART.
  • PL022 (synchronous serial port) for LCD module.
  • I2C audio output.
  • MicroSD card SPI adapter.
  • Ethernet using a memory-mapped interface.
  • VGA using a memory-mapped interface.
Arduino shield expansion for the MPS2+ platform The supported peripherals include:
  • GPIO.
  • Two SPI ports.
  • SPI for ADC.
  • Two I2C ports.
  • Three UART ports.


Cortex-M3 DesignStart Eval supports the V2M-MPS2+ FPGA platform, and not the V2M-MPS2 FPGA platform.

The uSDCard SPI adapter is included with newly purchased MPS2+ FPGA platforms and is also available for purchase from ARM to use with MPS2+ FPGA platforms that you already own.

The Arduino shield adapter board is not included with the MPS2+ FPGA platform, and can be purchased from ARM.

The design hierarchy places the peripherals according to the following groups:

  • Closely coupled peripherals, and the four primary GPIO peripherals.
  • MPS2+ board APB peripherals.
  • MPS2+ board external RAM components, and memory mapped devices that include two unused GPIO peripherals.

The following diagram shows the different peripheral groups:

Figure 3-3 Peripheral groups
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