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There are several APB master expansion ports from the IoT subsystem that are used for tightly coupled peripherals for application use.
These APB ports provide functions that are common to many SoC developments. These ports are shown in Figure 3-1 Cortex-M3 DesignStart Eval example system.
ARM recommends that you use three of the APB expansion ports with a cache (port 3), and embedded flash memory controller (ports 9 and 10). The design hierarchy instantiates m3ds_simple_flash as a wrapper for the AHB to SRAM instance. This wrapper provides access to the FLASH0 AHB port, and the APB ports. Therefore, a full embedded flash subsystem can be used as a drop-in replacement.
The other tightly coupled peripherals are: