6.3.6 Tarmac trace

If you run a simulation using the processor Cycle Model, you can configure the testbench to generate a Tarmac log file in the directory where the test runs.

The log file uses cycle counts as a timestamp, and prints the following information:

ITInstruction taken (condition code passed) with disassembly.
ISInstruction skipped (condition code failed) with disassembly.
RRegister update.
BBus access (instruction, data, or system bus).
MMemory access (duplicating bus accesses, all bus accesses are memory accesses).
EException information and events.

For more detailed explanation of the Tarmac trace format, see:

m3designstart/logical/testbench/execution_tb/tarmac.txt
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