4.3.1 Clock, reset, and user I/O signals

The following table displays the clock, reset, and user I/O signals:

Table 4-5 Clock, reset, and user I/O signals

Signal Direction Description
OSCCLK[0] Input Main clock at 50MHz.
OSCCLK[1] Input Main clock at 24.576MHz.
OSCCLK[2] Input Main clock at 25MHz.
CB_nPOR Input Powerup reset (active-LOW).
CB_nRST Input Reset (released after code download is done, active-LOW).
CLKOUT[1:0] Output PLL generated clock
CLKIN[1:0] Input Loop back clock from CLKOUT.
USER_LED[1:0] Output LEDs
USER_PB[1:0] Input Push buttons
EXP[51:0] Input and output I/O expansion port
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