4.1.3 External RAM, device, and system memory map

The following table shows the memory map for external RAM, devices, and system in Cortex®-M3 DesignStart™ Eval.

Table 4-3 External RAM, device, and system memory map

Type Start End Peripheral Size Subsystem connection Comment
External RAM 0x60000000 0x7FFFFFFF AHB expansion 512MB TARGEXP1 -
0x80000000 0x9FFFFFFF AHB expansion 512MB TARGEXP1 -
Device 0xA0000000 0xA000FFFF AHB expansion 64KB TARGEXP0 -
0xA0010000 0xBFFFFFFF AHB expansion - TARGEXP1 -
0xC0000000 0xDFFFFFFF AHB expansion 512MB TARGEXP1 -
System 0xE0000000 0xE0000FFF Instrumentation Trace Macrocell (ITM) 4KB Internal Private Peripheral Bus (PPB) -
System 0xE0001000 0xE0001FFF Data Watchpoint and Trace (DWT) 4KB Internal PPB -
System 0xE0002000 0xE0002FFF Flash Patch and Breakpoint (FPB) 4KB Internal PPB -
System 0xE0003000 0xE000DFFF Reserved - Internal PPB -
System 0xE000E000 0xE000EFFF System Control Space (SCS) 4KB Internal PPB -
System 0xE000F000 0xE003FFFF Reserved - Internal PPB -
System 0xE0040000 0xE0040FFF Trace Port Interface Unit (TPIU) 4KB Internal PPB Trace
System 0xE0041000 0xE0041FFF Embedded Trace Macrocell (ETM) 4KB Internal PPB Trace
System 0xE0042000 0xE00FEFFF Reserved - - -
System 0xE00FF000 0xE00FFFFF ROM table 4KB AHB Debug and trace
System 0xE0100000 0xFFFFFFFF AHB expansion - - -
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