3.3.1 Subsystem features

The features of the IoT subsystem in Cortex®-M3 DesignStart™ Eval include:

  • Instantiation of the Cortex-M3 processor with debug and trace.
  • Two Advanced Peripheral Bus (APB) timers.
  • A multi-layer AMBA AHB-Lite interconnect.
    • Two AHB-Lite slave expansion ports with access to the full peripheral and memory range.
    • Two AHB-Lite master expansion ports (one mapped to a 64KB region).
    • 14 APB4 master expansion ports (4KB address space each).
  • A memory system consisting of:
    • AHB-Lite master expansion and two APB4 master expansion ports dedicated for connection to a flash interface (on chip or external, and optionally with cache).
    • Static memory arranged in four banks of 32KB.

The IoT subsystem used for the example system in Cortex-M3 DesignStart Eval is a simplified version of CoreLink™ SSE-050. You can replace the subsystem with the full version of CoreLink SSE-050 for production. You can also create alternative subsystem designs that suit the needs of your application using the Cortex-M System Design Kit (CMSDK) components, which are included in Cortex-M3 DesignStart Eval. For more information on the CMSDK, see the ARM® Cortex®-M System Design Kit Technical Reference Manual.

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