3.2 Processor

The processor in ARM Cortex®-M3 DesignStart™ Eval is a fixed configuration of the Cortex-M3 processor. This enables easy evaluation access to the Cortex-M3 processor technology without the flexibility to configure the design, which is included in the full product.

The processor in Cortex-M3 DesignStart Eval is delivered in two alternative forms, which are the obfuscated RTL, and a Cycle Model.

Obfuscated RTL

The obfuscated RTL is used to rebuild an FPGA image of the system when a modification is done on the example system. Only a limited set of internal registers are exposed for debug purposes.

The obfuscated RTL of the processor is preconfigured, and it is a synthesizable Verilog version of the full Cortex-M3 processor. It is not intended for a production SoC, and does not show optimum performance if used for ASIC implementation evaluations.

Cycle Model
The Cycle Model of the processor includes visibility of the internal processor architectural registers, for simulation and debug purposes. The model is linked with your simulator during compilation. The model also generates a Tarmac log, which is a textual trace output file that contains all the instructions executed, and register and memory transactions.
This section contains the following subsections:
Non-ConfidentialPDF file icon PDF versionARM 100894_0000_00_en
Copyright © 2017 ARM Limited or its affiliates. All rights reserved.