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The processor in ARM Cortex®-M3 DesignStart™ Eval is a fixed configuration of the Cortex-M3 processor. This enables easy evaluation access to the Cortex-M3 processor technology without the flexibility to configure the design, which is included in the full product.
The processor in Cortex-M3 DesignStart Eval is delivered in two alternative forms, which are the obfuscated RTL, and a Cycle Model.
The obfuscated RTL is used to rebuild an FPGA image of the system when a modification is done on the example system. Only a limited set of internal registers are exposed for debug purposes.
The obfuscated RTL of the processor is preconfigured, and it is a synthesizable Verilog version of the full Cortex-M3 processor. It is not intended for a production SoC, and does not show optimum performance if used for ASIC implementation evaluations.