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|Home > Simulation and integration tests > Integration test list|
The Cortex®-M3 DesignStart™ Eval Execution Testbench provides a series of integration tests that you can run during simulation. These tests show that the deliverables have been set up correctly and demonstrate certain behaviors of the processor.
If a test does not pass, perform the following:
The tests provided are written in C or ARM assembly code using the CMSIS framework.
The following are the tests and their functions:
Table 6-1 Integration test list
Simple test to verify that the testbench is running correctly. Always check that this test passes when investigating any problem.
Simple benchmark example. You can manually measure the length of the test
loop by monitoring the
|apb_mux_tests||Detects the presence of various APB devices that are connected to the APB multiplexer.|
|cxdt||Demonstrate Serial Wire Debug functionality by reading the CoreSight ROM table to determine that components are present in the system.|
Tests the default slave activation.
default_slaves_tests accesses invalid memory locations.
|designtest_m3||Tests the following peripherals that are specific to the MPS2+
FPGA platform example system:
|dualtimer_demo||Demonstrates the features of APB dual timer.|
|gpio_driver_tests||Tests the GPIO device driver functions on GPIO0.|
|gpio_tests||Tests registers read and write, interrupt, masked access, and reserved register addresses for AHB GPIO0 to GPIO5.|
|interrupt_demo||Demonstrates the TIMER0 interrupt, GPIO0 interrupt, UART2 and UART3 interrupt.|
|memory_tests||Tests the system memory map.|
|rtx_demo||Demonstrates the Keil RTX Real-Time Operating System.|
|self_reset_demo||Demonstrates the SYSRESETREQ reset and lockup reset.|
Demonstrates the sleep features of:
|timer_driver_tests||Tests the timer device driver functions on TIMER0.|
|timer_tests||Tests the functionality of APB TIMER0 and TIMER1.|
|uart_driver_tests||Tests the UART device driver functions on UART2 and UART3.|
Tests the functionality of UART0 to UART4.
UART2 and 3 are connected in a cross arrangement in the testbench and the other UARTs are self-looped back.
|watchdog_demo||Demonstrates the APB watchdog.|