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Cortex®-M3 DesignStart™ Eval allows developers to easily develop and simulate SoC designs based on the ARM Cortex-M3 processor, and then perform hardware prototyping using an ARM Versatile Express Cortex-M Prototyping System (V2M-MPS2+) platform.
Cortex-M3 DesignStart Eval provides an example system that is built around the CoreLink™ SSE-050 subsystem, and the Cortex-M3 processor.
The example system includes all the standard components and peripherals for implementing a functioning ARM Cortex-M3 mbed™ OS endpoint device.
A fixed and preconfigured Cortex-M3 processor is delivered as obfuscated RTL, and a Cycle Model. Cortex-M3 DesignStart Eval does not support changing the configuration of the processor.
The obfuscated RTL is used to build an FPGA image when the Cortex-M3 DesignStart Eval system has been modified by the user. The obfuscated RTL only exposes a limited set of internal registers for debug purposes.
The processor Cycle Model is recommended for simulation and debug purposes. It includes visibility of the internal processor architectural registers.
The Cortex-M3 DesignStart Eval package includes:
For more details on how you are permitted to use these Cortex-M3 DesignStart Eval deliverables, see the ARM® Cortex®-M3 DesignStart™ Eval RTL and Testbench User Guide.