2.2.2 Compiling the RTL

To compile the RTL, follow these steps:

  1. Navigate to the following directory:
    <install_dir>/m3designstart/logical/testbench/execution_tb
  2. Clean any previous RTL compile by executing the following command:
    make clean
  3. Compile the RTL with the processor Cycle Model (DSM=yes), and specify the simulator that you are using with one of the following options:
    mtiMentor QuestaSim
    iusCadence IUS
    vcsSynopsys VCS
    For example, to compile using Synopsys VCS, execute the following command:
    make compile SIMULATOR=vcs DSM=yes

The compile log is written to <sim>_compile.log.

If the compilation is successful, then the following message is displayed:

>> Testbench compile with vcs and DSM=yes completed successfully, log in vcs_compile.log

If the compilation fails, then the following is displayed:

 >> ERROR: Testbench compile failed, check vcs_compile.log

Note:

If you want to compile the processor obfuscated RTL instead of the Cycle Model, then use DSM=no.

Non-ConfidentialPDF file icon PDF versionARM 100895_0000_00_en
Copyright © 2017 ARM Limited or its affiliates. All rights reserved.