|Non-Confidential||PDF version||ARM 100897_0000_00_en|
|Home > Customizations in the FPGA Evaluation Flow > Increasing the processor clock speed|
You can increase the Cortex®-M3 processor clock (SYSCLK) speed to meet your application requirements.
If you increase SYSCLK, then you are required to modify the following timing constraints file to reflect the new clock period constraints:
For more information on how to increase the core clock speed, see the ARM® Cortex®-M3 DesignStart™ Eval FPGA User Guide.
There are possible consequences to increasing the processor clock speed, such as meeting timing requirements. If it is not possible to meet timing at the new speed, then it is necessary to place register slices in the failing paths. However, these slices increase latency. The trade-off between clock speed and latency should be considered for optimum system performance.