4.2 Key points for ASIC implementation
Cortex®-M3 DesignStart™ Eval provides access to an RTL simulation and FPGA implementation flow only.
If you plan to take a design to an ASIC implementation, there are several factors to
- Cortex-M3 DesignStart Eval is not
representative of the full CoreLink™ SSE-050 and Cortex-M3
- Moving to an ASIC flow requires additional IPs, which include power
management, oscillators, memories, and the standard cells for the particular target
- A complete SoC requires the full power and reset sequence, which involves
several phases as power rails and oscillators become stable.
- The FPGA flow requires timing closure, but does not target an aggressive
implementation result. When a full clock and reset control structure is in place, the
process to achieve timing closure with satisfactory performance is likely to be more