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This book describes how to integrate peripherals, and make other modifications to the system delivered with Cortex®-M3 DesignStart™ Eval.
n identifier indicates the revision status of the product described in this book, for example, r
|r||Identifies the major revision of the product, for example, r1.|
|p||Identifies the minor revision or modification status of the product, for example, p2.|
This book is written for hardware engineers, system integrators, and system designers, who might not have previous experience of ARM products, but want to understand the process of generating their own customized system.
This book is organized into the following chapters:
This chapter introduces Cortex®-M3 DesignStart™ Eval, its features, and its documentation structure.
This chapter describes the typical customizations that can be made on the example system in Cortex®-M3 DesignStart™ Eval.
This chapter describes how to use Socrates™ to update the system.
This chapter describes the validation necessary for design changes, and the factors you must consider for ASIC implementation.
This chapter describes the typical customizations and the customization issues that might occur in the FPGA Evaluation Flow for Cortex®-M3 DesignStart™ Eval.
This appendix describes the technical changes between released issues of this book.
The ARM® Glossary is a list of terms used in ARM documentation, together with definitions for those terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning.
See the ARM® Glossary for more information.
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
The following figure explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation.
The signal conventions are:
The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means:
HIGH for active-HIGH signals.
LOW for active-LOW signals.
At the start or end of a signal name denotes an active-LOW signal.
This book contains information that is specific to this product. See the following documents for other relevant information.