5.1 FPGA flow

The FPGA flow in Cortex®-M3 DesignStart™ Eval does not rely on any particular FPGA or FPGA vendor features. Therefore, you can easily add functional blocks to the design, within the constraints of the MPS2+ FPGA platform (in particular, the 52 pins available for I/O expansion).

ARM does not support any modifications to the Motherboard Configuration Controller (MCC) firmware. The MCC preloads a code image using the SPI interface, configures the Real Time Clock (RTC), and accesses the SCC using the serial interface.

ARM recommends the following:

The implementation of Cortex-M3 DesignStart Eval on the MPS2+ platform only uses approximately 20% to 30% of the FPGA resources.

If you modify the FPGA design and include more peripheral logic, then the routing congestion increases. Depending on the specific design, if your FPGA resource utilization is approximately 90%, then it might start to become problematic. This can be offset by removing any unnecessary peripherals from the design.

The example system in Cortex-M3 DesignStart Eval does not include any clock domain bridges on the AHB, although each level of interconnect introduces a register slice. In a more complex design, it might be necessary to reduce the clock speed for some peripherals, or add further register slices.

Although the MPS2+ platform includes pins for expansion connectors, these pins are not designed for routing high-speed signals, which would be required for the expansion of the AHB interconnect. This might limit the expansion capabilities of the platform.

You are required to add any additional peripherals to the search path defined in the following file:


The Verilog structures used in the design for the FPGA should match the simulation environment, except for a few FPGA primitives used for IP pins and clocking.

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