2.1.3 Primary code memory

In the subsystem included with the Cortex®-M3 DesignStart™ Eval, there is a dedicated AHB interface that provides access to flash storage. This is connected in m3ds_user_partition using an AHB to SRAM interface to an FPGA block RAM.

The block RAM is preloaded in simulation with the executable code. When using the MPS2+ platform, code can also be executed from the 64-bit ZBT SSRAM1. If your development is focused on peripherals, then you can choose not to modify this code memory architecture. However, for an eventual SoC implementation, it will be necessary to replace the block RAM with a suitable equivalent, either SRAM or a flash interface.

If you want to optimize the performance of the flash interface using a cache, or intend to interface to an external flash memory, then you should replace the example components with your own design. There are three APB master interfaces on the subsystem which are reserved for memory expansion:

  • APB[3] is recommended to control a cache, if present.
  • APB[9] is recommended to control a flash interface, if present.
  • APB[10] is recommended to control a second bank of the flash interface, if present.

There are also two interrupts in the recommended mapping which a code memory interface can use. ARM recommends the following:

  • INTISR[32] to indicate a memory system fault.
  • INTISR[33] for the flash memory controller.
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