2.4 Multiple processor designs

Cortex®-M3 DesignStart™ Eval does not include support for designs with multiple processors.

However, it is possible to implement several Cortex-M3 processors in a single device by:

The CoreSight™ SoC deliverable can be licensed separately from ARM. It includes an alternative CORTEXM3INTEGRATIONCS level that has support for cross triggering, where the debug logic, Embedded Trace Macrocell (ETM) and Cross Trigger Interface (CTI) can interact with each other and with other CoreSight components. It also supports a full 32-pin Trace Port Interface Unit (TPIU), on-chip trace buffers, and trace capture into system memory with the appropriate IP.

If the Cortex-M3 processor does not match your application performance requirement, then you can consider licensing the full Cortex-M0 processor for lower power, or Cortex-M4 processor for more performance and DSP capabilities.

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