5.3.2 Code memory

The Cortex®-M3 processor begins code execution from address 0x00000000, which corresponds to the TARGETFLASH0 block RAM memory within the FPGA.

The Motherboard Configuration Controller (MCC) in the MPS2+ platform loads the code into the block RAM using SPI during the start-up sequence. If you are porting your design to a new platform, then either have a mechanism whereby a similar method can be used, or have the FPGA compiled with the appropriate block RAM initialized with the code contents.

Possible mechanisms for loading the code include:

  • Initializing the block RAM with a boot loader that redirects code execution to an external flash memory.
  • Remapping address 0x00000000 to an external flash device on the new platform.
  • Initializing the block RAM using a debugger every time the platform is initialized.
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