|Non-Confidential||PDF version||ARM 100897_0000_00_en|
|Home > Customizations in the FPGA Evaluation Flow > Porting to a different platform > Code memory|
The Cortex®-M3 processor begins code execution from address
0x00000000, which corresponds to the TARGETFLASH0 block RAM memory within the FPGA.
The Motherboard Configuration Controller (MCC) in the MPS2+ platform loads the code into the block RAM using SPI during the start-up sequence. If you are porting your design to a new platform, then either have a mechanism whereby a similar method can be used, or have the FPGA compiled with the appropriate block RAM initialized with the code contents.
Possible mechanisms for loading the code include:
0x00000000to an external flash device on the new platform.