5.3.1 FPGA platform clocks

Cortex®-M3 DesignStart™ Eval directly instantiates three Altera Cyclone V PLLs, which convert the input board clocks to the specific clocks needed.

For details of the input source clocks and the derived clocks from the PLLs, see the ARM® Cortex®-M3 DesignStart™ Eval FPGA User Guide.

The PLL instantiation is contained within the following file:

<install_directory>/smm/logical/smm_common_fpga/verilog/fpga_pll_speed.v

It is possible that the source clocks on a new platform do not match the source clocks on the MPS2+ platform. In this case, it is necessary to ensure that the newly selected PLLs are able to generate the required derived clock frequencies from the new platform’s source clocks. The minimum requirements are as follows:

  • PLL[0] is required to generate SYSCLK and the debug, SPI, and I2C clocks.
  • PLL[1] is required if there are audio peripherals.
  • PLL[2] is not currently used and so can be removed.
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