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There are four Advanced High-performance Bus (AHB) to SRAM interface modules that are instantiated within the subsystem hierarchy in the Cortex®-M3 DesignStart™ Eval. This multi-bank memory configuration gives the fastest possible access.
The IoT subsystem can be configured to provide 1, 2, 3 or 4 banks of SRAM. When you use the Cortex-M3 DesignStart Eval, any configuration is required to be made manually. However, there is limited value in modifying these SRAM interfaces when targeting an FPGA platform.