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Any changes with the integration within the example system in the Cortex®-M3 DesignStart™ Eval RTL require validation.
You can use the integration tests included with Cortex-M3 DesignStart Eval as an example of how to validate the integration in a structured way. For more information on integration tests, see the ARM® Cortex®-M3 DesignStart™ Eval RTL and Testbench User Guide.
Typically, a full stand-alone validation would have been performed on the peripherals that you integrate into a design. The focus at system level should be in testing the integration of all interfaces in all major operating modes, and demonstrating system-level functionality.
Any components that operate mainly through providing a system-level function, such as the Wake-up Interrupt Controller (WIC) and clock control logic, should be exercised in as many different system states as deemed practical.
If the components have specific throughput or latency requirements, you must demonstrate that they inter-operate as expected, and the worst-case performance is acceptable. For example, if the FPGA peripheral subsystem connects to the main subsystem AHB interconnect using an AHB matrix, it is important to demonstrate that they behave as expected. When only one peripheral is accessed at a time, usually from the processor, only a few cycles of latency is added. However, if there are also accesses coming from the subsystem AHB slave ports that are accessing different peripherals on the same matrix, then there will be additional stalls due to the port contention.