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The system register block provides a minimal set of registers.
This component only accepts word writes and aligned reads.
Table 3-6 System register block
||R/O||[31:0]||System ID Register|
||R/W||[7:0]||User Programmable Switches|
||R/W||[31:0]||System configuration data|
||R/W||[31:0]||System configuration control|
||R/W||[31:0]||System configuration status|
The System ID Register is divided into the following fields:
ID[27:16] HBI board number.
ID[15:12] Build variant. The value depends on the following command-line options:
--no-givc3command-line option is used.
--gicv3command-line option is used. This is the default.
ID[11:8] Platform type:
ID[7:0] FPGA build.
The System ID register is not implemented in the Foundation Model v1. All
unimplemented registers in the Foundation Model v1 system register block return the value
on reads. You can use this value to distinguish Foundation Model
v1 from both Foundation Model v2 and Foundation Platform v9, and FVP VE Base Platform.
The user-programmable Switches store 8 bits of state that can be read or
written by software on the platform. You can configure the startup value,
You can view and set the switches at run time from the web interface.
The LEDs store 8 bits of state that software can read or write on the platform and can be viewed at runtime from the web interface.
The system configuration control register provides two functions:
stops the simulation and returns control to the command line.
asserts and then clears the reset pins on all components in the simulation. It resets the system without clearing the contents of the RAMs.
DSBand infinite loop.
The system configuration data and status registers always return 0 on reads, and writes are ignored.