1.2 Arm®v8 64-bit architecture overview

The Arm®v8 architecture is both an extension and a successor to the Armv7 architecture.

Armv8 introduces two execution states:

AArch32 state is compatible with the Armv7‑A architecture. Code executing in AArch32 state can only use the A32 and T32 instruction sets, although in Armv8, these instruction sets have some new instructions relative to Armv7.

The AArch64 state introduces a new fixed-length 32-bit instruction set called A64, while maintaining support for the same architectural capabilities as Armv7‑A, such as TrustZone® and Virtualization. Code executing in AArch64 state can only use the A64 instruction set.

AArch64 has four Exception levels, EL0-EL3, that replace the eight processor modes in Armv7‑A:

Like Armv7‑A, AArch32 state includes 13 general registers, which are R0-R12, the Program Counter, R15, and two banked registers that contain the Stack Pointer, R13, and Link Register, R14. The User and System modes share these 16 registers and a Program Status Register (PSR). The new general purpose registers are all 64-bits wide to handle larger addresses, so 32-bit accesses use the lower halves of registers and either ignore or zero out the upper halves. The AArch32 registers map onto the lower halves of the AArch64 registers, and this permits AArch32 exceptions to be taken in AArch64 at a higher Exception level.

The two forms of instruction operate on either 32-bit or 64-bit values within the 64-bit general-purpose register file. Where a 32-bit instruction form is selected, the following holds true:

For more information about the Armv8 architecture, see the Arm®v8 Architecture Reference Manual.

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