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You can find information on the SPIs and PPIs on the GIC that the platform assigns.
The following table lists the SPI assignments.
Table 3-4 Shared peripheral interrupt assignments
IRQ ID | SPI offset | Device |
---|---|---|
32 | 0 | Watchdog, SP805 |
34 | 2 | Dual-Timer 0, SP804 |
35 | 3 | Dual-Timer 1, SP804 |
36 | 4 | Realtime Clock, PL031 |
37 | 5 | UART0, PL011 |
38 | 6 | UART1, PL011 |
39 | 7 | UART2, PL011 |
40 | 8 | UART3, PL011 |
41 | 9 | MCI, PL180, MCIINTR0 |
46 | 14 | PL111 CLCD |
47 | 15 | Ethernet, SMSC 91C111 |
56 | 24 | Trusted Watchdog, SP085 |
57 | 25 | AP_REFCLK, Generic Timer, CNTPSIRQ |
58 | 26 | AP_REFCLK, Generic Timer, CNTPSIRQ1 |
59 | 27 | EL2 Generic Watchdog WS0 |
60 | 28 | EL2 Generic Watchdog WS1 |
74 | 42 | Virtio block device |
75 | 43 | Virtio Plan 9 |
76 | 44 | Virtio net device |
92 | 60 | cpu0 PMUIRQ |
93 | 61 | cpu1 PMUIRQ |
94 | 62 | cpu2 PMUIRQ |
95 | 63 | cpu3 PMUIRQ |
The following table shows the PPI assignments:
Table 3-5 Private Peripheral Interrupt map
PPI | Device |
---|---|
3 | Secure hypervisor virtual timer event |
4 | Secure hypervisor physical timer event |
9 | Virtual maintenance interrupt |
10 | Hypervisor timer event |
11 | Virtual timer event |
12 | Hypervisor virtual timer event |
13 | Secure physical timer event |
14 | Non-secure physical timer event |