3.5 System register block

The system register block provides a minimal set of registers.

This component only accepts word writes and aligned reads.

Table 3-6 System register block

Offset Type Bits Register
0x0000 R/O [31:0] System ID Register
0x0004 R/W [7:0] User Programmable Switches
0x0008 R/W [7:0] LEDs
0x00A0 R/W [31:0] System configuration data
0x00A4 R/W [31:0] System configuration control
0x00A8 R/W [31:0] System configuration status

The System ID Register is divided into the following fields:

  • ID[31:28] Revision.

    Foundation Platform v9.1-v9.5.
    Foundation Platform v9.6.
  • ID[27:16] HBI board number.

    Arm®v8‑A Foundation Platform, default.
    Arm Base Platform FVP.
  • ID[15:12] Build variant. The value depends on the following command-line options:

    Variant A is the Foundation Platform with the GICv2 legacy map, when the --no-givc3 command-line option is used.
    Variant B is the Foundation Platform with the GICv3 64KB memory map, when the --gicv3 command-line option is used. This is the default.
  • ID[11:8] Platform type:

    Model, default.
  • ID[7:0] FPGA build.

    • Not used.

The System ID register is not implemented in the Foundation Model v1. All unimplemented registers in the Foundation Model v1 system register block return the value 0xDEADDEAD on reads. You can use this value to distinguish Foundation Model v1 from both Foundation Model v2 and Foundation Platform v9, and FVP VE Base Platform.

The user-programmable Switches store 8 bits of state that can be read or written by software on the platform. You can configure the startup value, val, using --switches=val.

You can view and set the switches at run time from the web interface.

The LEDs store 8 bits of state that software can read or write on the platform and can be viewed at runtime from the web interface.

The system configuration control register provides two functions:

  • Writing the value 0xC0800000 stops the simulation and returns control to the command line.
  • Writing the value 0xC0900000 asserts and then clears the reset pins on all components in the simulation. It resets the system without clearing the contents of the RAMs.


Writes to the system configuration register can take several instructions to complete. Therefore, a write to this register must be followed by a DSB and infinite loop.

The system configuration data and status registers always return 0 on reads, and writes are ignored.

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