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This section describes the methods in the
CADI class that provide the main interfaces for configuring and running the target.
This section describes common aspects of the methods in the CADI class.
For more details of the structs, enums, and defines that the CADI interface uses, see also the CADITypes.h file.
If called, unsupported methods must return
The setup API controls the interaction between the host, the debugger, and the CADI target.
Use this API to:
The breakpoint API enables defining various types of breakpoint in the target model.
The types of breakpoint:
This section describes what the execution API enables a debugger to do.
The register API exposes the internal state of the registers of a model for inspection and modification.
If a model has a large number of registers, the registers can be grouped to simplify navigating through the registers. The register API supports compound registers.
Models must expose their internal performance counters (for example, Instr Cache Reads, Instr Cache Misses) as registers to be accessible through this interface.
The memory API exposes the internal state of the memory of a model for inspection and modification. Memory is exposed through address spaces (memory spaces) that represent separately addressable units.
For processor models, the memory exposed through the API is not memory contained in the model, but rather memory accessed by the model.
Some processor models, however, do contain their own physical memory and expose this memory as a separate memory space.
The requirement for multiple memory spaces is because of different processor models:
Memory models typically expose a single memory space corresponding to their physical memory and other models typically do not expose any memory.
Data stored in a memory space is organized according to the endianness specified by the flags of that particular memory space. This can be little endian or big endian, with the invariance defining the number of bytes in an accessed unit.
Data can also be organized using a model-specific endianness. In these cases, the documentation that accompanies the model must provide specific details.
The total number of bytes in a memory word can be determined
bitsPerMau. The bytes are divided in
invariance bytes. These groups are
then arranged in little endian or big endian order.
For example, for
invariance of 2 and
b0 b1 b2 b3 b4 b5 b6 b7.
b6 b7 b4 b5 b2 b3 b0 b1.
Each memory space can be subdivided in memory blocks. Memory blocks contain additional information pertaining to the intended usage of the memory. This information can be used as hints for memory data presentation dedicated for human consumption, but it has no effect on the actual simulation.
These functions enable access to cache memories in the target.
CADIGetCacheInfo() function to return the cache information for
the target. The
functions are used to directly access the cache memory contents.
This section describes what the parameters API enables.