B.3.3 Thread-aware breakpoints using CONTEXTIDR

ARM targets support thread-aware breakpoints by matching the threadID field against the 32-bit CONTEXTIDR register in the target.

Targets must indicate support for this mechanism by including the string threadID=CONTEXTIDR in the extendedTargetFeatures register as an nExtendedTargetFeaturesRegNum entry.

Using this mechanism, whenever a breakpoint condition is met and bit 31 of conditionOperator field is set, the threadID field is compared against CONTEXTIDR. If threadID and CONTEXTIDR are equal, the breakpoint hits. If they differ, the breakpoint does not hit and is ignored. If bit 31 of conditionOperator is 0, the threadID field is ignored.

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