A.8.51 Special purpose registers with permanent breakpoints for vector catching with CADIBptGetList()

Fast Models enables vector catching, using permanent breakpoints on special purpose registers. CADIBptGetList() returns these breakpoints, if present, in addition to temporary ones.

Table A-1 Cortex®-A and R special purpose registers with permanent breakpoints

Cortex-A and Cortex-R TrustZone® (Non-secure) TrustZone (Monitor) Virtualization
RESET - - -
UNDEFINED NS_UNDEFINED - HYP_UNDEFINED
- - - HYP_HYP
SVC NS_SVC SMC HVC
PREFETCH_ABORT NS_PREFETCH_ABORT MON_PREFETCH_ABORT HYP_PREFETCH_ABORT
DATA_ABORT NS_DATA_ABORT MON_DATA_ABORT HYP_DATA_ABORT
IRQ NS_IRQ MON_IRQ HYP_IRQ
FIQ NS_FIQ MON_FIQ HYP_FIQ

Table A-2 Cortex-A and R special purpose registers with permanent breakpoints unique to AArch64 processors

EL + descriptor, for example S_EL1_CURRENT_SP0_SYNC.
Exception levels Descriptor
S_EL1 NS_EL1 EL2 EL3 _CURRENT_SP0_SYNC
S_EL1 NS_EL1 EL2 EL3 _CURRENT_SP0_IRQ
S_EL1 NS_EL1 EL2 EL3 _CURRENT_SP0_FIQ
S_EL1 NS_EL1 EL2 EL3 _CURRENT_SP0_ABORT
S_EL1 NS_EL1 EL2 EL3 _CURRENT_SPx_SYNC
S_EL1 NS_EL1 EL2 EL3 _CURRENT_SPx_IRQ
S_EL1 NS_EL1 EL2 EL3 _CURRENT_SPx_FIQ
S_EL1 NS_EL1 EL2 EL3 _CURRENT_SPx_ABORT
S_EL1 NS_EL1 EL2 EL3 _LOWER_64_SYNC
S_EL1 NS_EL1 EL2 EL3 _LOWER_64_IRQ
S_EL1 NS_EL1 EL2 EL3 _LOWER_64_FIQ
S_EL1 NS_EL1 EL2 EL3 _LOWER_64_ABORT
S_EL1 NS_EL1 EL2 EL3 _LOWER_32_SYNC
S_EL1 NS_EL1 EL2 EL3 _LOWER_32_IRQ
S_EL1 NS_EL1 EL2 EL3 _LOWER_32_FIQ
S_EL1 NS_EL1 EL2 EL3 _LOWER_32_ABORT

Table A-3 Cortex-M special purpose registers with permanent breakpoints, for exceptions

If TrustZone is not present If TrustZone is present
RESET RESET
LOCKUP Secure_LOCKUP
IRQa Secure_IRQ and Non_Secure_IRQb
NMI Secure_NMI and Non_Secure_NMI
HARDFAULT Secure_HARDFAULT and Non_Secure_HARDFAULT
MEMMANAGE Secure_MEMMANAGE and Non_Secure_MEMMANAGE
BUSFAULT Secure_BUSFAULT and Non_Secure_BUSFAULT
USGFAULT Secure_USGFAULT and Non_Secure_USGFAULT
SVCALL Secure_SVCALL and Non_Secure_SVCALL
DEBUG_MONITOR Secure_DEBUG_MONITOR and Non_Secure_DEBUG_MONITOR
PENDSV Secure_PENDSV and Non_Secure_PENDSV
- SECUREFAULT
SYSTICK Secure_SYSTICK and Non_Secure_SYSTICK

Table A-4 Cortex-M special purpose registers with permanent breakpoints, exception returns

If TrustZone is not present If TrustZone is present
RETURN_LOCKUP Secure_RETURN_LOCKUP
RETURN_IRQc Secure_RETURN_IRQ and Non_Secure_RETURN_IRQd
RETURN_NMI Secure_RETURN_NMI and Non_Secure_RETURN_NMI
RETURN_HARDFAULT Secure_RETURN_HARDFAULT and Non_Secure_RETURN_HARDFAULT
RETURN_MEMMANAGE Secure_RETURN_MEMMANAGE and Non_Secure_RETURN_MEMMANAGE
RETURN_BUSFAULT Secure_RETURN_BUSFAULT and Non_Secure_RETURN_BUSFAULT
RETURN_USGFAULT Secure_RETURN_USGFAULT and Non_Secure_RETURN_USGFAULT
RETURN_SVCALL Secure_RETURN_SVCALL and Non_Secure_RETURN_SVCALL
RETURN_DEBUG_MONITOR Secure_RETURN_DEBUG_MONITOR and Non_Secure_RETURN_DEBUG_MONITOR
RETURN_PENDSV Secure_RETURN_PENDSV and Non_Secure_RETURN_PENDSV
- RETURN_SECUREFAULT
RETURN_SYSTICK Secure_RETURN_SYSTICK and Non_Secure_RETURN_SYSTICK
a Catches all IRQs. To catch a specific IRQ, use register IRQn, where n is the IRQ number. These numbered registers do not have variants for different security states or for catching exception returns.
b Catch all Secure_IRQs or Non_Secure_IRQs. To catch a specific IRQ, use register IRQn, where n is the IRQ number. These numbered registers do not have variants for different security states or for catching exception returns.
c Catches all IRQ returns.
d Catch all Secure_IRQ or Non_Secure_IRQ returns.
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