Fast Models Reference Manual

Version 11.2


Table of Contents

Preface
About this book
Using this book
Glossary
Typographic conventions
Feedback
Other information
1 Introduction
1.1 About the models
1.2 Model capabilities
1.3 Fast Models accuracy
1.3.1 How accurate are Fast Models?
1.3.2 Timing accuracy of Fast Models
1.3.3 Bus traffic in Fast Models
1.3.4 Instruction prefetch in Fast Models
1.3.5 Out-of-order execution and write-buffers in Fast Models
1.3.6 Caches in Fast Models
1.3.7 Global exclusive monitor in Fast Models
1.4 Processor implementation
1.4.1 Caches in PV models
1.4.2 GICv3 in PV models
1.4.3 CP14 Debug coprocessor
1.4.4 MicroTLBs
1.4.5 TLBs in PV models
1.4.6 Memory access in PV models
1.4.7 Timing in PV models
1.4.8 VIC ports in PV models
1.5 Fast Models CADI implementation
1.6 CADI interactions with processor behavior
1.7 CADI sync watchpoints
1.8 Non-CADI sync watchpoints
1.8.1 syncLevel definitions
1.8.2 Controlling and observing the syncLevel
1.9 SCADI
1.9.1 About SCADI
1.9.2 Intended uses of CADI and SCADI
1.9.3 Responsibilities of the SCADI caller
1.9.4 SCADI interface access
1.9.5 SCADI semantics
1.10 Checkpoints
1.11 Using the TelnetTerminal
1.12 Network set up
1.12.1 User mode networking
1.12.2 TAP/TUN networking
1.13 Model Trace Interface
1.14 Using parameters to set port values
2 Protocols
2.1 AMBA-PV protocols
2.1.1 AMBA-PV protocols - about
2.1.2 AMBAPV protocol
2.1.3 AMBAPVACE protocol
2.1.4 AMBAPVSignal protocol
2.1.5 AMBAPVSignalState protocol
2.1.6 AMBAPVValue protocol
2.1.7 AMBAPVValue64 protocol
2.1.8 AMBAPVValueState protocol
2.1.9 AMBAPVValueState64 protocol
2.2 Clocking protocols
2.2.1 Clocking protocols - about
2.2.2 ClockRateControl protocol
2.2.3 TimerCallback protocol
2.2.4 TimerCallback64 protocol
2.2.5 TimerControl protocol
2.2.6 TimerControl64 protocol
2.3 Debug interface protocols
2.3.1 Debug interface protocols - about
2.3.2 CADIDisassemblerProtocol protocol
2.3.3 CADIProtocol protocol
2.4 Peripheral protocols
2.4.1 AudioControl protocol
2.4.2 CharacterLCD protocol
2.4.3 FlashLoaderPort protocol
2.4.4 GUIPollCallback protocol
2.4.5 ICS307Configuration protocol
2.4.6 KeyboardStatus protocol
2.4.7 LCD protocol
2.4.8 LCDLayoutInfo protocol
2.4.9 MMC_Protocol protocol
2.4.10 MouseStatus protocol
2.4.11 PL080_DMAC_DmaPortProtocol protocol
2.4.12 PS2Data protocol
2.4.13 PVBusSlaveControl protocol
2.4.14 PVDevice protocol
2.4.15 PVTransactionMaster protocol
2.4.16 SerialData protocol
2.4.17 SMMUv3AEMIdentifyProtocol protocol
2.4.18 TZFilterControl protocol
2.4.19 VirtualEthernet protocol
2.5 Power management protocols
2.5.1 PChannel protocol
2.6 Processor protocols
2.6.1 CounterInterface protocol
2.6.2 GICv3Comms protocol
2.6.3 InstructionCount protocol
2.6.4 v8EmbeddedCrossTrigger_controlprotocol protocol
2.7 Signaling protocols
2.7.1 Signaling protocols - about
2.7.2 Signal protocol
2.7.3 StateSignal protocol
2.7.4 Value protocol
2.7.5 Value_64 protocol
2.7.6 ValueState protocol
3 Processor Components
3.1 About the processor components
3.2 Cortex®‑A processor components
3.2.1 ARMAEMv8AMPCT component
3.2.2 ARMCortexA75xnCT component
3.2.3 ARMCortexA73xnCT component
3.2.4 ARMCortexA72xnCT component
3.2.5 ARMCortexA57xnCT component
3.2.6 ARMCortexA55CT_CortexA75CT component
3.2.7 ARMCortexA55xnCT component
3.2.8 ARMCortexA53xnCT component
3.2.9 ARMCortexA35xnCT component
3.2.10 ARMCortexA32xnCT component
3.2.11 ARMCortexA17xnCT component
3.2.12 ARMCortexA15xnCT component
3.2.13 ARMCortexA12xnCT component
3.2.14 ARMCortexA9MPxnCT component
3.2.15 ARMCortexA9UPCT component
3.2.16 ARMCortexA8CT component
3.2.17 ARMCortexA7xnCT component
3.2.18 ARMCortexA5MPxnCT component
3.2.19 ARMCortexA5CT component
3.3 Cortex®‑R processor components
3.3.1 ARMCortexR52xnCT component
3.3.2 ARMCortexR8xnCT component
3.3.3 ARMCortexR7xnCT component
3.3.4 ARMCortexR5xnCT component
3.3.5 ARMCortexR4CT component
3.4 Cortex®‑M processor components
3.4.1 ARMAEMv8MCT component
3.4.2 ARMCortexM33CT component
3.4.3 ARMCortexM23CT component
3.4.4 ARMCortexM7CT component
3.4.5 ARMCortexM4CT component
3.4.6 ARMCortexM3CT component
3.4.7 ARMCortexM0PlusCT component
3.4.8 ARMCortexM0CT component
3.4.9 ARMSC000CT component
3.4.10 ARMSC300CT component
3.5 Classic processor components
3.5.1 ARM1176CT component
3.5.2 ARM1136CT component
3.5.3 ARM968CT component
3.5.4 ARM926CT component
4 Peripheral and Interface Components
4.1 Peripheral and interface components - about
4.2 AMBA-PV components
4.2.1 AMBA-PV components - about
4.2.2 PVBus2AMBAPV component
4.2.3 AMBAPV2PVBus component
4.2.4 PVBus2AMBAPVACE component
4.2.5 AMBAPVACE2PVBus component
4.2.6 SGSignal2AMBAPVSignal component
4.2.7 AMBAPVSignal2SGSignal component
4.2.8 SGStateSignal2AMBAPVSignalState component
4.2.9 AMBAPVSignalState2SGStateSignal component
4.2.10 SGValue2AMBAPVValue component
4.2.11 SGValue2AMBAPVValue64 component
4.2.12 AMBAPVValue2SGValue component
4.2.13 AMBAPVValue2SGValue64 component
4.2.14 SGValueState2AMBAPVValueState component
4.2.15 SGValueState2AMBAPVValueState64 component
4.2.16 AMBAPVValueState2SGValueState component
4.2.17 AMBAPVValueState2SGValueState64 component
4.3 Clocking components
4.3.1 Clocking components - about
4.3.2 ClockDivider component
4.3.3 ClockTimer component
4.3.4 ClockTimer64 component
4.3.5 MasterClock component
4.4 Peripheral components
4.4.1 AndGate component
4.4.2 AudioOut_File component
4.4.3 AudioOut_SDL component
4.4.4 BP135_AXI2APB component
4.4.5 BP141_TZMA component
4.4.6 BP147_TZPC component
4.4.7 CCI400 component
4.4.8 CCI500 component
4.4.9 CCI550 component
4.4.10 CCN502 component
4.4.11 CCN504 component
4.4.12 CCN508 component
4.4.13 CCN512 component
4.4.14 CMN-600 component
4.4.15 DMC_400 component
4.4.16 DMC500 component
4.4.17 DMC520 component
4.4.18 DMC620 component
4.4.19 DP500 component
4.4.20 DP500x2 component
4.4.21 DP550 component
4.4.22 DP550x2 component
4.4.23 DP650 component
4.4.24 DP650x2 component
4.4.25 DummyAPB component
4.4.26 ElfLoader component
4.4.27 FlashLoader component
4.4.28 GenericTimer component
4.4.29 GIC_400 component
4.4.30 GIC500 component
4.4.31 GIC500_Filter component
4.4.32 GIC600 component
4.4.33 GIC600_Filter component
4.4.34 GICv3IRI component
4.4.35 GICv3IRI_Filter component
4.4.36 HostBridge component
4.4.37 ICS307 component
4.4.38 IDAU component
4.4.39 IntelStrataFlashJ3 component
4.4.40 Mali_G71 component
4.4.41 Mali-V550 component
4.4.42 Mali-V61 component
4.4.43 MemoryMappedCounterModule component
4.4.44 MemoryMappedGenericWatchdog component
4.4.45 MMC component
4.4.46 MMU_400 component
4.4.47 MMU_500 component
4.4.48 MMU_600 component
4.4.49 OrGate component
4.4.50 PL011_Uart component
4.4.51 PL022_SSP component
4.4.52 PL030_RTC component
4.4.53 PL031_RTC component
4.4.54 PL041_AACI component
4.4.55 PL050_KMI component
4.4.56 PL061_GPIO component
4.4.57 PL080_DMAC component
4.4.58 PL110_CLCD component
4.4.59 PL111_CLCD component
4.4.60 PL180_MCI component
4.4.61 PL192_VIC component
4.4.62 PL310_L2CC component
4.4.63 PL330_DMAC component
4.4.64 PL340_DMC component
4.4.65 PL350_SMC component
4.4.66 PL350_SMC_NAND_FLASH component
4.4.67 PL370_HDLCD component
4.4.68 PL390_GIC component
4.4.69 PPUv1 component
4.4.70 PS2Keyboard component
4.4.71 PS2Mouse component
4.4.72 RAMDevice component
4.4.73 RemapDecoder component
4.4.74 SerialCrossover component
4.4.75 SMMUv3AEM component
4.4.76 SMSC_91C111 component
4.4.77 SP804_Timer component
4.4.78 SP805_Watchdog component
4.4.79 SP810_SysCtrl component
4.4.80 TelnetTerminal component
4.4.81 TZC_400 component
4.4.82 TZIC component
4.4.83 v8EmbeddedCrossTrigger_Interface component
4.4.84 v8EmbeddedCrossTrigger_Matrix component
4.4.85 VirtioBlockDevice component
4.4.86 VirtioNetMMIO component
4.4.87 VirtioP9Device component
4.4.88 VirtualEthernetCrossover component
4.4.89 VMIDFilter component
4.5 PVBus components
4.5.1 About PVBus components
4.5.2 About PVBus system components
4.5.3 PVBus Transaction Master ID
4.5.4 PVBus examples
4.5.5 PVBusDecoder component
4.5.6 PVBusMapper component
4.5.7 PVBusMaster component
4.5.8 PVBusRange component
4.5.9 PVBusSlave component
4.5.10 TZSwitch component
4.5.11 Labeller and LabellerForDMA330 components
4.5.12 LabellerForGPUProtMode component
4.5.13 PVBus C++ transaction and Tx_Result classes
4.6 Visualisation Library
4.6.1 Visualisation Library - about
4.6.2 LISA Visualisation models
4.6.3 GUIPoll component
4.6.4 Visualisation Library C++ classes
5 Trace Components in Fast Models
5.1 ARM_AEMv8-A_MP - trace
5.2 ARM_AEMv8M - trace
5.3 ARM_ARM1136JF-S - trace
5.4 ARM_ARM1176JZF-S - trace
5.5 ARM_ARM926EJ-S - trace
5.6 ARM_ARM968E-S - trace
5.7 ARM_Cortex-A15 - trace
5.8 ARM_Cortex-A17 - trace
5.9 ARM_Cortex-A32 - trace
5.10 ARM_Cortex-A35 - trace
5.11 ARM_Cortex-A5 - trace
5.12 ARM_Cortex-A53 - trace
5.13 ARM_Cortex-A55 - trace
5.14 ARMCortexA55CT_CortexA75CT - trace
5.15 ARM_Cortex-A57 - trace
5.16 ARM_Cortex-A5MP - trace
5.17 ARM_Cortex-A7 - trace
5.18 ARM_Cortex-A72 - trace
5.19 ARM_Cortex-A73 - trace
5.20 ARM_Cortex-A75 - trace
5.21 ARM_Cortex-A8 - trace
5.22 ARM_Cortex-A9MP - trace
5.23 ARM_Cortex-A9UP - trace
5.24 ARM_Cortex-M0 - trace
5.25 ARM_Cortex-M0+ - trace
5.26 ARM_Cortex-M23 - trace
5.27 ARM_Cortex-M3 - trace
5.28 ARM_Cortex-M33 - trace
5.29 ARM_Cortex-M4 - trace
5.30 ARM_Cortex-M7 - trace
5.31 ARM_Cortex-R4 - trace
5.32 ARM_Cortex-R5 - trace
5.33 ARM_Cortex-R7 - trace
5.34 ARM_Cortex-R8 - trace
5.35 ARM_CortexR52 - trace
5.36 ARM_SC000 - trace
5.37 ARM_SC300 - trace
5.38 ARMv8Cluster - trace
5.39 AsyncCacheFlushUnit - trace
5.40 Base_PowerController - trace
5.41 CCI400 - trace
5.42 CCI500 - trace
5.43 CCI550 - trace
5.44 CCNCache - trace
5.45 CCNRegisterSet - trace
5.46 CMN600 - trace
5.47 CMN600Cache - trace
5.48 DMC-500 - trace
5.49 DMC-520 - trace
5.50 DMC-620 - trace
5.51 DP500 - trace
5.52 DP550 - trace
5.53 DP650 - trace
5.54 GIC_400 - trace
5.55 GICv2 - trace
5.56 GICv3CPUInterface - trace
5.57 GICv3CPUInterfaceDecoder - trace
5.58 GICv3Distributor - trace
5.59 GICv3IRI - trace
5.60 GICv3InterruptTranslationService - trace
5.61 GICv3ProtocolChecker - trace
5.62 GICv3Redistributor - trace
5.63 GICv3RedistributorInternal - trace
5.64 MMU_400_BASE - trace
5.65 MMU_500_BASE - trace
5.66 MMU_600 - trace
5.67 Mali_G71 - trace
5.68 MemoryMappedCounterModule - trace
5.69 PL011_Uart - trace
5.70 PL11x_CLCD - trace
5.71 PL330_DMAC - trace
5.72 PPUv1 - trace
5.73 PVBus2AMBAPVACE - trace
5.74 PVBusBridge - trace
5.75 PVBusExclusiveMonitor - trace
5.76 PVBusLogger - trace
5.77 PVBusMapper - trace
5.78 PVBusMaster - trace
5.79 PVBusSlave - trace
5.80 PVCache - trace
5.81 RAMDevice - trace
5.82 TCM - trace
5.83 TLB - trace
5.84 V550 - trace
5.85 V61 - trace
5.86 VirtioBlockDevice - trace
5.87 VirtioP9Device - trace
5.88 VirtualEthernetCrossover - trace
6 Plug-ins for Fast Models
6.1 Loading a plug-in into a model
6.2 ArchMsgTrace
6.2.1 ArchMsgTrace parameters
6.3 CADIIPCRemoteConnection
6.3.1 CADIIPCRemoteConnection parameters
6.4 Fastline
6.4.1 Profiling Fast Models
6.4.2 Cluster configuration file format
6.4.3 System configuration file format
6.4.4 Counter configuration file format
6.4.5 Fastline parameters
6.5 GDBRemoteConnection
6.5.1 GDBRemoteConnection parameters
6.5.2 GDBRemoteConnection limitations
6.6 GenericCounter
6.6.1 GenericCounter parameters
6.7 GenericTrace
6.7.1 GenericTrace parameters
6.8 LinuxSyscallTrace
6.8.1 LinuxSyscallTrace parameters
6.9 ListTraceSources
6.9.1 ListTraceSources parameters
6.10 PipelineModel
6.10.1 PipelineModel example
6.10.2 PipelineModel parameters
6.10.3 Naming the plug-in instance
6.10.4 Example command lines
6.10.5 PipelineModel output
6.11 RunTimeParameterTest
6.12 ScalableVectorExtension
6.12.1 ScalableVectorExtension parameters
6.13 Sidechannel
6.14 TarmacText
6.14.1 TarmacText parameters
6.15 TarmacTrace
6.15.1 TarmacTrace parameters
6.15.2 TarmacTrace file format
7 SystemC Example Platforms
7.1 About example systems
7.2 Building the examples
7.3 Running the examples
7.4 Instantiating a big.LITTLE™ example
7.5 Instantiating a CustomScheduler example
7.6 Instantiating a Dhrystone example
7.7 Instantiating a DMA example
7.8 Instantiating a DMADhrystone example
7.9 Instantiating a DualDhrystone example
7.10 Instantiating a GlobalInterface example
7.11 Instantiating a LinuxBoot example
8 Base Platform
8.1 Base - about
8.2 Base Platform RevC changes
8.3 BasePlatformPCIRevC component
8.4 Base - memory
8.4.1 Base - secure memory
8.4.2 Base - memory map
8.4.3 Base - DRAM
8.5 Base - interrupt assignments
8.6 Base - clocks
8.7 Base - parameters
8.8 Base - components
8.8.1 Base - components - about
8.8.2 Base - Base_PowerController component
8.8.3 Base - DebugAccessPort component
8.8.4 Base - simulator visualization component
8.8.5 Base - VE_SysRegs component
8.9 Base - differences between the AEMv8-A FVP and core FVPs
8.10 Base - VE compatibility
8.10.1 Base - VE compatibility - GICv2
8.10.2 Base - VE compatibility - GICv3
8.10.3 Base - VE compatibility - system global counter
8.10.4 Base - VE compatibility - disable security
8.11 Base - unsupported VE features
8.11.1 Base - unsupported VE features - memory aliasing at 0x08_00000000
8.11.2 Base - unsupported VE features - boot ROM alias at 0x00_0800_0000
8.11.3 Base - unsupported VE features - change of older parameters
9 Microcontroller Prototyping System 2
9.1 MPS2 - about
9.2 MPS2 platform types
9.3 MPS2 - memory maps
9.3.1 MPS2 - memory map for models without the Arm®v8‑M additions
9.3.2 MPS2 - memory map for models with the Arm®v8‑M additions
9.4 MPS2 - interrupt assignments
9.5 MPS2 - differences between models and hardware
10 Versatile Express Model
10.1 About the Versatile Express baseboard components
10.2 VE memory map for Cortex®‑A series
10.3 VE memory map for Cortex®‑R series
10.4 VE - interrupt assignments for Cortex®‑A series
10.5 VE - interrupt assignments for Cortex®‑R series
10.6 VE parameters
10.6.1 VE instantiation parameters
10.6.2 VE secure memory parameters
10.6.3 VE switch S6
10.7 VEVisualisation component
10.7.1 VEVisualisation - about
10.7.2 VEVisualisation - ports
10.7.3 VEVisualisation - parameters
10.7.4 VEVisualisation - verification and testing
10.7.5 VEVisualisation - performance
10.7.6 VEVisualisation - library dependencies
10.8 VE_SysRegs component
10.8.1 VE_SysRegs - about
10.8.2 VE_SysRegs - ports
10.8.3 VE_SysRegs - parameters
10.8.4 VE_SysRegs - registers
10.8.5 VE_SysRegs - verification and testing
10.9 Differences between the VE hardware and the system model
10.9.1 Memory map
10.9.2 Memory aliasing
10.9.3 VE hardware features absent
10.9.4 VE hardware features different
10.9.5 Restrictions on the processor models
10.9.6 Timing considerations for the VE FVPs

Release Information

Document History
Issue Date Confidentiality Change
A 31 May 2014 Non-Confidential New document for Fast Models v9.0, from DUI0423Q for v8.3.
B 30 November 2014 Non-Confidential Update for v9.1.
C 28 February 2015 Non-Confidential Update for v9.2.
D 31 May 2015 Non-Confidential Update for v9.3.
E 31 August 2015 Non-Confidential Update for v9.4.
F 30 November 2015 Non-Confidential Update for v9.5.
G 29 February 2016 Non-Confidential Update for v9.6.
H 31 May 2016 Non-Confidential Update for v10.0.
I 31 August 2016 Non-Confidential Update for v10.1.
J 11 November 2016 Non-Confidential Update for v10.2.
K 17 February 2017 Non-Confidential Update for v10.3.
1100-00 31 May 2017 Non-Confidential Update for v11.0. Document numbering scheme has changed.
1101-00 31 August 2017 Non-Confidential Update for v11.1.
1102-00 17 November 2017 Non-Confidential Update for v11.2.

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