Fast Models Reference Manual

Version 11.4


Table of Contents

Preface
About this book
Using this book
Glossary
Typographic conventions
Feedback
Other information
1 Introduction
1.1 About the models
1.2 Model capabilities
1.3 Fast Models accuracy
1.3.1 How accurate are Fast Models?
1.3.2 Timing accuracy of Fast Models
1.3.3 Bus traffic in Fast Models
1.3.4 Instruction prefetch in Fast Models
1.3.5 Out-of-order execution and write-buffers in Fast Models
1.3.6 Caches in Fast Models
1.3.7 Global exclusive monitor in Fast Models
1.4 Processor implementation
1.4.1 Caches in PV models
1.4.2 GICv3 in PV models
1.4.3 CP14 Debug coprocessor
1.4.4 MicroTLBs
1.4.5 TLBs in PV models
1.4.6 Memory access in PV models
1.4.7 Timing in PV models
1.4.8 VIC ports in PV models
1.5 Fast Models CADI implementation
1.6 CADI interactions with processor behavior
1.7 CADI sync watchpoints
1.8 Non-CADI sync watchpoints
1.8.1 syncLevel definitions
1.8.2 Controlling and observing the syncLevel
1.9 SCADI
1.9.1 About SCADI
1.9.2 Intended uses of CADI and SCADI
1.9.3 Responsibilities of the SCADI caller
1.9.4 SCADI interface access
1.9.5 SCADI semantics
1.10 Checkpoints
1.11 Using the TelnetTerminal
1.12 Network set up
1.12.1 User mode networking
1.12.2 TAP/TUN networking
1.13 Model Trace Interface
1.14 Using parameters to set port values
1.15 About PVBus system components
1.16 PVBus C++ transaction and Tx_Result classes
1.16.1 Class pv::TransactionGenerator
1.16.2 TransactionGenerator efficiency considerations
1.16.3 Enum pv::AccessWidth
1.16.4 Class pv::Transaction
1.16.5 Class pv::ReadTransaction
1.16.6 Class pv::WriteTransaction
1.17 Visualisation Library
1.17.1 Visualisation Library - about
1.17.2 LISA Visualisation models
1.17.3 Visualisation Library C++ classes
2 Protocols
2.1 AMBA-PV protocols
2.1.1 AMBA-PV protocols - about
2.1.2 AMBAPV protocol
2.1.3 AMBAPVACE protocol
2.1.4 AMBAPVSignal protocol
2.1.5 AMBAPVSignalState protocol
2.1.6 AMBAPVValue protocol
2.1.7 AMBAPVValue64 protocol
2.1.8 AMBAPVValueState protocol
2.1.9 AMBAPVValueState64 protocol
2.2 Clocking protocols
2.2.1 Clocking protocols - about
2.2.2 ClockRateControl protocol
2.2.3 TimerCallback protocol
2.2.4 TimerCallback64 protocol
2.2.5 TimerControl protocol
2.2.6 TimerControl64 protocol
2.3 Debug interface protocols
2.3.1 Debug interface protocols - about
2.3.2 CADIDisassemblerProtocol protocol
2.3.3 CADIProtocol protocol
2.4 Peripheral protocols
2.4.1 AudioControl protocol
2.4.2 CharacterLCD protocol
2.4.3 FlashLoaderPort protocol
2.4.4 GUIPollCallback protocol
2.4.5 ICS307Configuration protocol
2.4.6 KeyboardStatus protocol
2.4.7 LCD protocol
2.4.8 LCDLayoutInfo protocol
2.4.9 MMC_Protocol protocol
2.4.10 MouseStatus protocol
2.4.11 PL080_DMAC_DmaPortProtocol protocol
2.4.12 PS2Data protocol
2.4.13 PVBusSlaveControl protocol
2.4.14 PVDevice protocol
2.4.15 PVTransactionMaster protocol
2.4.16 SerialData protocol
2.4.17 SMMUv3AEMIdentifyProtocol protocol
2.4.18 TZFilterControl protocol
2.4.19 VirtualEthernet protocol
2.5 Power management protocols
2.5.1 PChannel protocol
2.6 Processor protocols
2.6.1 CounterInterface protocol
2.6.2 GICv3Comms protocol
2.6.3 InstructionCount protocol
2.6.4 v8EmbeddedCrossTrigger_controlprotocol protocol
2.7 Signaling protocols
2.7.1 Signaling protocols - about
2.7.2 Signal protocol
2.7.3 StateSignal protocol
2.7.4 Value protocol
2.7.5 Value_64 protocol
2.7.6 ValueState protocol
3 Fast Models components
3.1 Bridge components
3.1.1 AMBAPV2PVBus
3.1.2 AMBAPV2PVBusx4
3.1.3 AMBAPV2PVBusx8
3.1.4 AMBAPVACE2PVBus
3.1.5 AMBAPVSignal2SGSignal
3.1.6 AMBAPVSignal2SGSignalx16
3.1.7 AMBAPVSignal2SGSignalx224
3.1.8 AMBAPVSignal2SGSignalx4
3.1.9 AMBAPVSignal2SGSignalx48
3.1.10 AMBAPVSignal2SGSignalx8
3.1.11 AMBAPVSignal2SGSignalx988
3.1.12 AMBAPVSignalState2SGStateSignal
3.1.13 AMBAPVSignalState2SGStateSignalx4
3.1.14 AMBAPVValue2SGValue
3.1.15 AMBAPVValue2SGValue64
3.1.16 AMBAPVValue2SGValue64x4
3.1.17 AMBAPVValue2SGValuex4
3.1.18 AMBAPVValue642SMMUv3AEMIdentify
3.1.19 AMBAPVValueState2SGValueState
3.1.20 AMBAPVValueState2SGValueState64
3.1.21 AMBAPVValueState2SGValueState64x4
3.1.22 AMBAPVValueState2SGValueStatex4
3.1.23 BroadcastSignal2AMBAPVSignal
3.1.24 Clock2SystemC
3.1.25 CounterInterface2SystemC
3.1.26 InstructionCount2SystemC
3.1.27 InstructionCount2SystemCx4
3.1.28 LCD2SystemC
3.1.29 PChannel2SystemC
3.1.30 PVBus2AMBAPV
3.1.31 PVBus2AMBAPVACE
3.1.32 PVBus2AMBAPVx4
3.1.33 PVBus2AMBAPVx8
3.1.34 PVBusBridge
3.1.35 SGSignal2AMBAPVSignal
3.1.36 SGSignal2AMBAPVSignalx16
3.1.37 SGSignal2AMBAPVSignalx224
3.1.38 SGSignal2AMBAPVSignalx256
3.1.39 SGSignal2AMBAPVSignalx4
3.1.40 SGSignal2AMBAPVSignalx48
3.1.41 SGSignal2AMBAPVSignalx8
3.1.42 SGStateSignal2AMBAPVSignalState
3.1.43 SGStateSignal2AMBAPVSignalStatex4
3.1.44 SGValue2AMBAPVValue
3.1.45 SGValue2AMBAPVValue64
3.1.46 SGValue2AMBAPVValue64x4
3.1.47 SGValue2AMBAPVValuex4
3.1.48 SGValueState2AMBAPVValueState
3.1.49 SGValueState2AMBAPVValueState64
3.1.50 SGValueState2AMBAPVValueState64x4
3.1.51 SGValueState2AMBAPVValueStatex4
3.1.52 SMMUv3AEMIdentify2AMBAPVValue64
3.1.53 SystemC2Clock
3.1.54 SystemC2InstructionCount
3.1.55 SystemC2InstructionCountx4
3.1.56 SystemC2InstructionCountx8
3.1.57 SystemC2LCD
3.1.58 SystemC2PChannel
3.1.59 SystemC2VirtualEthernet
3.1.60 SystemC2v7VGICConfig
3.1.61 VirtualEthernet2SystemC
3.1.62 v7VGICConfig2SystemC
3.2 Bus components
3.2.1 MSIRewriter
3.2.2 PVBusCache
3.2.3 PVBusDecoder
3.2.4 PVBusExclusiveMonitor
3.2.5 PVBusExclusiveSquasher
3.2.6 PVBusLogger
3.2.7 PVBusMapper
3.2.8 PVBusMaster
3.2.9 PVBusModifier
3.2.10 PVBusModifierx2
3.2.11 PVBusRouter
3.2.12 PVBusSlave
3.2.13 PVWriteBuffer
3.2.14 SimplePVBusMaster
3.2.15 TZSwitch
3.3 Clocking components
3.3.1 ClockDivider
3.3.2 ClockTimer
3.3.3 ClockTimer64
3.3.4 ClockTimerThread
3.3.5 ClockTimerThread64
3.3.6 MasterClock
3.4 Core components
3.4.1 ARMAEMv8AMPCT
3.4.2 ARMAEMv8A_AEMv8AMPCT
3.4.3 ARMAEMv8MCT
3.4.4 ARMCortexA15x1CT
3.4.5 ARMCortexA17x1CT
3.4.6 ARMCortexA32x1CT
3.4.7 ARMCortexA35x1CT
3.4.8 ARMCortexA53x1CT
3.4.9 ARMCortexA55CT
3.4.10 ARMCortexA55CT_CortexA75CT
3.4.11 ARMCortexA55CT_CortexA76CT
3.4.12 ARMCortexA55x1CT_CortexA75x1CT
3.4.13 ARMCortexA55x4CT_CortexA76x2CT
3.4.14 ARMCortexA57x1CT
3.4.15 ARMCortexA5CT
3.4.16 ARMCortexA5MPx1CT
3.4.17 ARMCortexA72x1CT
3.4.18 ARMCortexA73x1CT
3.4.19 ARMCortexA75CT
3.4.20 ARMCortexA76CT
3.4.21 ARMCortexA7x1CT
3.4.22 ARMCortexA8CT
3.4.23 ARMCortexA9MPx1CT
3.4.24 ARMCortexA9UPCT
3.4.25 ARMCortexM0CT
3.4.26 ARMCortexM0PlusCT
3.4.27 ARMCortexM23CT
3.4.28 ARMCortexM33CT
3.4.29 ARMCortexM35PCT
3.4.30 ARMCortexM3CT
3.4.31 ARMCortexM4CT
3.4.32 ARMCortexM7CT
3.4.33 ARMCortexR4CT
3.4.34 ARMCortexR52x1CT
3.4.35 ARMCortexR5x1CT
3.4.36 ARMCortexR7x1CT
3.4.37 ARMCortexR8x1CT
3.4.38 ARMSC000CT
3.4.39 ARMSC300CT
3.5 Media components
3.5.1 D71
3.5.2 DP500
3.5.3 DP500x2
3.5.4 DP550
3.5.5 DP550x2
3.5.6 DP650
3.5.7 DP650x2
3.5.8 V550
3.5.9 V61
3.6 Other components
3.6.1 AsyncSignal
3.6.2 GICv3CommsLogger
3.6.3 SchedulerInterface
3.6.4 SchedulerThread
3.6.5 SchedulerThreadEvent
3.7 Peripheral components
3.7.1 AudioOut_File
3.7.2 AudioOut_SDL
3.7.3 Base_PowerController
3.7.4 DMC620
3.7.5 DebugAccessPort
3.7.6 DebugROM
3.7.7 DualClusterSystemConfigurationBlock
3.7.8 DummyAPB
3.7.9 ElfLoader
3.7.10 FlashLoader
3.7.11 GIC500_ClusterPorts
3.7.12 GICv3CommsPVBus
3.7.13 GICv3ProtocolChecker
3.7.14 GUIPoll
3.7.15 HostBridge
3.7.16 HostSerialInterface
3.7.17 IntelStrataFlashJ3
3.7.18 MemoryMappedGenericTimer
3.7.19 MemoryMappedGenericWatchdog
3.7.20 NonVolatileCounter
3.7.21 PPUMultiThreadModeSwitch
3.7.22 PS2Keyboard
3.7.23 PS2Mouse
3.7.24 PVBusGICv3Comms
3.7.25 RAMDevice
3.7.26 RandomNumberGenerator
3.7.27 RealTimeLimiter
3.7.28 RealtimeClockTimer
3.7.29 RemapDecoder
3.7.30 RootKeyStorage
3.7.31 SerialCrossover
3.7.32 TelnetTerminal
3.7.33 UnusedPrimeCell
3.7.34 VirtioBlockDevice
3.7.35 VirtioNetMMIO
3.7.36 VirtioP9Device
3.7.37 VirtioPCIBlockDevice
3.7.38 VirtualEthernetCrossover
3.7.39 VirtualEthernetHub3
3.7.40 VisEventRecorder
3.7.41 WarningMemory
3.7.42 v8EmbeddedCrossTrigger_Interface
3.7.43 v8EmbeddedCrossTrigger_Matrix
3.8 Signals components
3.8.1 AndGate
3.8.2 LabellerUserSignals
3.8.3 OrGate
3.8.4 SGSignalBuffer
3.8.5 SGSignalBufferx16
3.8.6 SGSignalBufferx2
3.8.7 SGSignalBufferx4
3.8.8 SGSignalBufferx8
3.8.9 SGSignalBufferx988
3.8.10 SignalLogger
3.8.11 Value64Logger
3.8.12 ValueLogger
3.9 SystemIP components
3.9.1 AHCI_SATA
3.9.2 BP141_TZMA
3.9.3 BP147_TZPC
3.9.4 CCI400
3.9.5 CCI500
3.9.6 CCI550
3.9.7 CCN502
3.9.8 CCN504
3.9.9 CCN508
3.9.10 CCN512
3.9.11 CMN600
3.9.12 CMN600CMLHub
3.9.13 DMC500
3.9.14 DMC520
3.9.15 DMC_400
3.9.16 GIC500
3.9.17 GIC500_Filter
3.9.18 GIC600
3.9.19 GIC600_Filter
3.9.20 GIC_400
3.9.21 GICv3IRI
3.9.22 GICv3IRI_Filter
3.9.23 ICS307
3.9.24 IDAU
3.9.25 MMC
3.9.26 MMU_400
3.9.27 MMU_400_BASE
3.9.28 MMU_500
3.9.29 MMU_500_BASE
3.9.30 MMU_600
3.9.31 MemoryMappedCounterModule
3.9.32 MessageHandlingUnitV2
3.9.33 PL011_Uart
3.9.34 PL022_SSP
3.9.35 PL030_RTC
3.9.36 PL031_RTC
3.9.37 PL041_AACI
3.9.38 PL050_KMI
3.9.39 PL061_GPIO
3.9.40 PL080_DMAC
3.9.41 PL110_CLCD
3.9.42 PL111_CLCD
3.9.43 PL180_MCI
3.9.44 PL192_VIC
3.9.45 PL310_L2CC
3.9.46 PL330_DMAC
3.9.47 PL350_SMC
3.9.48 PL350_SMC_NAND_FLASH
3.9.49 PL370_HDLCD
3.9.50 PL390_GIC
3.9.51 PPUMTWakerequest
3.9.52 PPUv0
3.9.53 PPUv1
3.9.54 PPUv1_Cluster_Wakerequest_Logic
3.9.55 SMMUv3AEM
3.9.56 SMSC_91C111
3.9.57 SP804_Timer
3.9.58 SP805_Watchdog
3.9.59 SP810_SysCtrl
3.9.60 TZC_400
3.9.61 TZFilterUnit
3.9.62 TZIC
3.9.63 v7_VGIC
4 Trace components
4.1 AHCI_SATA - trace
4.2 AMBAPVSignal2SGSignalx8 - trace
4.3 ARMAEMv8AMPCT - trace
4.4 ARMAEMv8A_AEMv8AMPCT - trace
4.5 ARMCortexA32x1CT - trace
4.6 ARMCortexA35x1CT - trace
4.7 ARMCortexA53x1CT - trace
4.8 ARMCortexA55CT - trace
4.9 ARMCortexA55CT_CortexA75CT - trace
4.10 ARMCortexA55CT_CortexA76CT - trace
4.11 ARMCortexA55x1CT_CortexA75x1CT - trace
4.12 ARMCortexA55x4CT_CortexA76x2CT - trace
4.13 ARMCortexA57x1CT - trace
4.14 ARMCortexA72x1CT - trace
4.15 ARMCortexA73x1CT - trace
4.16 ARMCortexA75CT - trace
4.17 ARMCortexA76CT - trace
4.18 ARM_AEMv8-A_MP - trace
4.19 ARM_AEMv8M - trace
4.20 ARM_Cortex-A15 - trace
4.21 ARM_Cortex-A17 - trace
4.22 ARM_Cortex-A32 - trace
4.23 ARM_Cortex-A35 - trace
4.24 ARM_Cortex-A5 - trace
4.25 ARM_Cortex-A53 - trace
4.26 ARM_Cortex-A55 - trace
4.27 ARM_Cortex-A57 - trace
4.28 ARM_Cortex-A5MP - trace
4.29 ARM_Cortex-A7 - trace
4.30 ARM_Cortex-A72 - trace
4.31 ARM_Cortex-A73 - trace
4.32 ARM_Cortex-A75 - trace
4.33 ARM_Cortex-A76 - trace
4.34 ARM_Cortex-A8 - trace
4.35 ARM_Cortex-A9MP - trace
4.36 ARM_Cortex-A9UP - trace
4.37 ARM_Cortex-M0 - trace
4.38 ARM_Cortex-M0+ - trace
4.39 ARM_Cortex-M23 - trace
4.40 ARM_Cortex-M3 - trace
4.41 ARM_Cortex-M33 - trace
4.42 ARM_Cortex-M35P - trace
4.43 ARM_Cortex-M4 - trace
4.44 ARM_Cortex-M7 - trace
4.45 ARM_Cortex-R4 - trace
4.46 ARM_Cortex-R5 - trace
4.47 ARM_Cortex-R7 - trace
4.48 ARM_Cortex-R8 - trace
4.49 ARM_CortexR52 - trace
4.50 ARM_SC000 - trace
4.51 ARM_SC300 - trace
4.52 ARMv8Cluster - trace
4.53 AsyncCacheFlushUnit - trace
4.54 Base_PowerController - trace
4.55 CCI400 - trace
4.56 CCI500 - trace
4.57 CCI550 - trace
4.58 CCNCache - trace
4.59 CCNRegisterSet - trace
4.60 CMN600 - trace
4.61 CMN600Cache - trace
4.62 D71 - trace
4.63 DMC-500 - trace
4.64 DMC-520 - trace
4.65 DMC-620 - trace
4.66 DP500 - trace
4.67 DP550 - trace
4.68 DP650 - trace
4.69 DualClusterSystemConfigurationBlock - trace
4.70 GIC_400 - trace
4.71 GICv2 - trace
4.72 GICv3CPUInterface - trace
4.73 GICv3CPUInterfaceDecoder - trace
4.74 GICv3CommsLogger - trace
4.75 GICv3CommsPVBus - trace
4.76 GICv3Distributor - trace
4.77 GICv3IRI - trace
4.78 GICv3InterruptTranslationService - trace
4.79 GICv3ProtocolChecker - trace
4.80 GICv3Redistributor - trace
4.81 GICv3RedistributorInternal - trace
4.82 MMU_400_BASE - trace
4.83 MMU_500_BASE - trace
4.84 MMU_600 - trace
4.85 MSIRewriter - trace
4.86 MemoryMappedCounterModule - trace
4.87 MessageHandlingUnitV2 - trace
4.88 NonVolatileCounter - trace
4.89 PL011_Uart - trace
4.90 PL11x_CLCD - trace
4.91 PL330_DMAC - trace
4.92 PPUv0 - trace
4.93 PPUv1 - trace
4.94 PVBus2AMBAPVACE - trace
4.95 PVBusBridge - trace
4.96 PVBusExclusiveMonitor - trace
4.97 PVBusGICv3Comms - trace
4.98 PVBusLogger - trace
4.99 PVBusMapper - trace
4.100 PVBusMaster - trace
4.101 PVBusSlave - trace
4.102 PVCache - trace
4.103 PVWriteBuffer - trace
4.104 RAMDevice - trace
4.105 SMMUv3AEM - trace
4.106 SignalLogger - trace
4.107 TLB - trace
4.108 V550 - trace
4.109 V61 - trace
4.110 Value64Logger - trace
4.111 ValueLogger - trace
4.112 VirtioBlockDevice - trace
4.113 VirtioP9Device - trace
4.114 VirtioPCIBlockDevice - trace
4.115 VirtualEthernetCrossover - trace
4.116 atc - trace
4.117 v7_VGIC - trace
5 Plug-ins for Fast Models
5.1 Loading a plug-in into a model
5.2 ArchMsgTrace
5.2.1 ArchMsgTrace parameters
5.3 CADIIPCRemoteConnection
5.3.1 CADIIPCRemoteConnection parameters
5.4 Fastline
5.4.1 Profiling Fast Models
5.4.2 Cluster configuration file format
5.4.3 System configuration file format
5.4.4 Counter configuration file format
5.4.5 Fastline parameters
5.5 GDBRemoteConnection
5.5.1 GDBRemoteConnection parameters
5.5.2 GDBRemoteConnection limitations
5.6 GenericCounter
5.6.1 GenericCounter parameters
5.7 GenericTrace
5.7.1 GenericTrace parameters
5.8 LinuxSyscallTrace
5.8.1 LinuxSyscallTrace parameters
5.9 ListTraceSources
5.9.1 ListTraceSources parameters
5.10 PipelineModel
5.10.1 PipelineModel example
5.10.2 PipelineModel parameters
5.10.3 Naming the plug-in instance
5.10.4 Example command lines
5.10.5 PipelineModel output
5.11 RunTimeParameterTest
5.12 ScalableVectorExtension
5.12.1 ScalableVectorExtension parameters
5.13 Sidechannel
5.14 TarmacText
5.14.1 TarmacText parameters
5.15 TarmacTrace
5.15.1 TarmacTrace parameters
5.15.2 TarmacTrace file format
5.15.3 Instruction trace
5.15.4 Program flow trace
5.15.5 Register trace
5.15.6 Cache maintenance trace
5.15.7 Cache content trace
5.15.8 Translation table walk trace
5.15.9 TLB trace
5.15.10 Event trace
5.15.11 Processor memory access trace
5.15.12 Processor memory update trace
5.15.13 Memory bus trace
5.15.14 Tarmac Trace output example
6 SystemC Example Platforms
6.1 About example systems
6.2 Building the examples
6.3 Running the examples
6.4 Instantiating a big.LITTLE™ example
6.5 Instantiating a CustomScheduler example
6.6 Instantiating a Dhrystone example
6.7 Instantiating a DMA example
6.8 Instantiating a DMADhrystone example
6.9 Instantiating a DualDhrystone example
6.10 Instantiating a GlobalInterface example
6.11 Instantiating a LinuxBoot example
7 Base Platform
7.1 Base - about
7.2 Base Platform RevC changes
7.3 BasePlatformPCIRevC component
7.4 Base - memory
7.4.1 Base - secure memory
7.4.2 Base - memory map
7.4.3 Base - DRAM
7.5 Base - interrupt assignments
7.6 Base - clocks
7.7 Base - parameters
7.8 Base - components
7.8.1 Base - components - about
7.8.2 Base - Base_PowerController component
7.8.3 Base - DebugAccessPort component
7.8.4 Base - simulator visualization component
7.8.5 Base - VE_SysRegs component
7.9 Base - differences between the AEMv8-A FVP and core FVPs
7.10 Base - VE compatibility
7.10.1 Base - VE compatibility - GICv2
7.10.2 Base - VE compatibility - GICv3
7.10.3 Base - VE compatibility - system global counter
7.10.4 Base - VE compatibility - disable security
7.11 Base - unsupported VE features
7.11.1 Base - unsupported VE features - memory aliasing at 0x08_00000000
7.11.2 Base - unsupported VE features - boot ROM alias at 0x00_0800_0000
7.11.3 Base - unsupported VE features - change of older parameters
8 Microcontroller Prototyping System 2
8.1 MPS2 - about
8.2 MPS2 platform types
8.3 MPS2 - memory maps
8.3.1 MPS2 - memory map for models without the Armv8‑M additions
8.3.2 MPS2 - memory map for models with the Armv8‑M additions
8.4 MPS2 - interrupt assignments
8.5 MPS2 - differences between models and hardware
9 Versatile Express Model
9.1 About the Versatile Express baseboard components
9.2 VE memory map for Cortex®‑A series
9.3 VE memory map for Cortex®‑R series
9.4 VE - interrupt assignments for Cortex®‑A series
9.5 VE - interrupt assignments for Cortex®‑R series
9.6 VE parameters
9.6.1 VE instantiation parameters
9.6.2 VE secure memory parameters
9.6.3 VE switch S6
9.7 VEVisualisation component
9.7.1 VEVisualisation - about
9.7.2 VEVisualisation - ports
9.7.3 VEVisualisation - parameters
9.7.4 VEVisualisation - verification and testing
9.7.5 VEVisualisation - performance
9.7.6 VEVisualisation - library dependencies
9.8 VE_SysRegs component
9.8.1 VE_SysRegs - about
9.8.2 VE_SysRegs - ports
9.8.3 VE_SysRegs - parameters
9.8.4 VE_SysRegs - registers
9.8.5 VE_SysRegs - verification and testing
9.9 Differences between the VE hardware and the system model
9.9.1 Memory map
9.9.2 Memory aliasing
9.9.3 VE hardware features absent
9.9.4 VE hardware features different
9.9.5 Restrictions on the processor models
9.9.6 Timing considerations for the VE FVPs

Release Information

Document History
Issue Date Confidentiality Change
A 31 May 2014 Non-Confidential New document for Fast Models v9.0, from DUI0423Q for v8.3.
B 30 November 2014 Non-Confidential Update for v9.1.
C 28 February 2015 Non-Confidential Update for v9.2.
D 31 May 2015 Non-Confidential Update for v9.3.
E 31 August 2015 Non-Confidential Update for v9.4.
F 30 November 2015 Non-Confidential Update for v9.5.
G 29 February 2016 Non-Confidential Update for v9.6.
H 31 May 2016 Non-Confidential Update for v10.0.
I 31 August 2016 Non-Confidential Update for v10.1.
J 11 November 2016 Non-Confidential Update for v10.2.
K 17 February 2017 Non-Confidential Update for v10.3.
1100-00 31 May 2017 Non-Confidential Update for v11.0. Document numbering scheme has changed.
1101-00 31 August 2017 Non-Confidential Update for v11.1.
1102-00 17 November 2017 Non-Confidential Update for v11.2.
1103-00 23 February 2018 Non-Confidential Update for v11.3.
1104-00 22 June 2018 Non-Confidential Update for v11.4.

Non-Confidential Proprietary Notice

This document is protected by copyright and other related rights and the practice or implementation of the information contained in this document may be protected by one or more patents or pending patent applications. No part of this document may be reproduced in any form by any means without the express prior written permission of Arm. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated.

Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations infringe any third party patents.

THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, SATISFACTORY QUALITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE WITH RESPECT TO THE DOCUMENT. For the avoidance of doubt, Arm makes no representation with respect to, and has undertaken no analysis to identify or understand the scope and content of, third party patents, copyrights, trade secrets, or other rights.

This document may include technical inaccuracies or typographical errors.

TO THE EXTENT NOT PROHIBITED BY LAW, IN NO EVENT WILL ARM BE LIABLE FOR ANY DAMAGES, INCLUDING WITHOUT LIMITATION ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, ARISING OUT OF ANY USE OF THIS DOCUMENT, EVEN IF ARM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

This document consists solely of commercial items. You shall be responsible for ensuring that any use, duplication or disclosure of this document complies fully with any relevant export laws and regulations to assure that this document or any portion thereof is not exported, directly or indirectly, in violation of such export laws. Use of the word “partner” in reference to Arm’s customers is not intended to create or refer to any partnership relationship with any other company. Arm may make changes to this document at any time and without notice.

If any of the provisions contained in these terms conflict with any of the provisions of any click through or signed written agreement covering this document with Arm, then the click through or signed written agreement prevails over and supersedes the conflicting provisions of these terms. This document may be translated into other languages for convenience, and you agree that if there is any conflict between the English version of this document and any translation, the terms of the English version of the Agreement shall prevail.

The Arm corporate logo and words marked with ® or ™ are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. Other brands and names mentioned in this document may be the trademarks of their respective owners. Please follow Arm’s trademark usage guidelines at http://www.arm.com/company/policies/trademarks.

Copyright © 2014–2018 Arm Limited (or its affiliates). All rights reserved.

Arm Limited. Company 02557590 registered in England.

110 Fulbourn Road, Cambridge, England CB1 9NJ.

LES-PRE-20349

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to.

Unrestricted Access is an Arm internal classification.

Product Status

The information in this document is Final, that is for a developed product.

Web Address

Non-ConfidentialPDF file icon PDF version100964_1104_00_en
Copyright © 2014–2018 Arm Limited or its affiliates. All rights reserved.