3.4.29 ARMCortexM0PlusCT

ARMCortexM0PlusCT CPU component. This model is written in C++ and models version r0p1 of the RTL.

ARMCortexM0PlusCT contains the following CADI targets:

  • ARM_Cortex-M0+

ARMCortexM0PlusCT contains the following MTI components:

Differences between the model and the RTL

  • This model does not have a parameter that is equivalent to the RAR integration option. The architecturally required register state is reset.

  • Arm does not guarantee that all Arm®v7‑M behavior is absent from models of Armv6‑M cores. As a consequence, Arm does not guarantee that code that runs on Armv7‑M cores but fails on Armv6‑M cores also fails on Armv6‑M Fast Models cores.

Table 3-150 Ports

Name Protocol Type Description
ahbd PVBus Slave Debug AHB - core bus slave driven by the DAP.
bigend Signal Slave Configure big endian data format.
clk_in ClockSignal Slave The clock signal connected to the clk_in port is used to determine the rate at which the core executes instructions.
currpri Value Master Current execution priority.
edbgrq Signal Slave External debug request.
event Signal Peer This peer port of event input (and output) is for wakeup from WFE and corresponds to the RTL TXEV and RXEV signals.
intisr[32] Signal Slave This signal array delivers signals to the NVIC.
intnmi Signal Slave Configure non maskable interrupt.
io_port_in PVBus Slave I/O port pair. See the documentation for the io_port_out port.
io_port_out PVBus Master I/O port pair. Used if IOP is true. Transactions from io_port_out which do not "match" should be returned via io_port_in. For performance reasons, the I/O port interface is not modelled directly. Instead, a simple PVBus gasket is inserted at the point in the memory system where the I/O port would be. In hardware, a device would be attached to the port which would tell the CPU whether it would like to intercept each transaction, given its address. This can be modelled in a performant manner by connecting a PVBusMapper-based device to io_port_out which intercepts transactions of interest and passes other transactions back to the CPU via io_port_in. Your I/O port device model is also responsible for aborting transactions which would be aborted on hardware (e.g. exclusives) if necessary.
lockup Signal Master Asserted when the processor is in lockup state.
poreset Signal Slave Raising this signal will do a power-on reset of the core.
pv_ppbus_m PVBus Master The core will generate External Private Peripheral Bus requests on this port.
pvbus_m PVBus Master The core will generate bus requests on this port.
sleepdeep Signal Master Asserted when the processor is in deep sleep.
sleeping Signal Master Asserted when the processor is in sleep.
stcalib Value Slave This is the calibration value for the SysTick timer.
stclk ClockSignal Slave This is the reference clock for the SysTick timer.
sysreset Signal Slave Raising this signal will put the core into reset mode (but does not reset the debug logic).
sysresetreq Signal Master Asserted to indicate that a reset is required.
ticks InstructionCount Master Port allowing the number of instructions since startup to be read from the CPU.

Table 3-151 Parameters for ARM_Cortex-M0plus

Name Type Default value Description
BIGENDINIT bool 0x0 Initialize processor to big endian mode
BKPT int 0x4 Number of breakpoint unit comparators implemented
DBG bool 0x1 Set whether debug extensions are implemented
IOP bool 0x0 Send all d-side transactions to the port, io_port_out. Transactions which do not match should be returned to the port, io_port_in
IRQDIS int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n]
NUM_IRQ int 0x20 Number of user interrupts
NUM_MPU_REGION int 0x0 Number of MPU regions
SYST bool 0x1 Enable support for SysTick timer functionality
USER bool 0x1 Enable support for Unprivileged/Privileged Extension
VTOR bool 0x1 Include Vector Table Offset Register
WIC bool 0x1 Include support for WIC-mode deep sleep
WPT int 0x2 Number of watchpoint unit comparators implemented
cpi_div int 0x1 divider for calculating CPI (Cycles Per Instruction)
cpi_mul int 0x1 multiplier for calculating CPI (Cycles Per Instruction)
master_id int 0x0 Master ID presented in bus transactions
min_sync_level int 0x0 force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
scheduler_mode int 0x0 Control the interleaving of instructions in this processor (0=default long quantum, 1=low latency mode, short quantum and signal checking, 2=lock-breaking mode, long quantum with additional context switches near load-exclusive instructions, 3=ISSCompare)
semihosting-Thumb_SVC int 0xab T32 SVC number for semihosting
semihosting-cmd_line string "" Command line available to semihosting SVC calls
semihosting-cwd string "" Base directory for semihosting file access.
semihosting-enable bool 0x1 Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
semihosting-heap_base int 0x0 Virtual address of heap base
semihosting-heap_limit int 0x10700000 Virtual address of top of heap
semihosting-prefix bool 0x0 Prefix semihosting output with target instance name
semihosting-stack_base int 0x10700000 Virtual address of base of descending stack
semihosting-stack_limit int 0x10800000 Virtual address of stack limit
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