3.8.1 AndGate

And Gate. This model is written in LISA+.

AndGate contains the following CADI targets:

  • AndGate

About AndGate

This component implements a logical AND of two signal input ports to generate a single output signal. For example, you can use it to combine two interrupt signals.

Table 3-278 Ports

Name Protocol Type Description
input[2] Signal Slave 2 input signals to be AND'ed.
output Signal Master AND'ed output signal.
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