3.5.3 DP500x2

ARM DP500 Display Processor x2. This model is written in LISA+.

DP500x2 contains the following CADI targets:

  • DP500
  • DP500x2

DP500x2 contains the following MTI components:

About DP500x2

This component is a model of the dual display configuration of the DP500 Display Processor, with basic support for the display and scaling engines. Connect it to a visualization component to view LCD output.

The model provides the following functionality:

  • All RGB and YUV format parsing.
  • Color adjustment in Display Engine (DE).
  • Nearest neighbor scaling.
  • All layers.
  • Alpha blending.
  • Memory writeback.
  • Inverse gamma adjustment.
  • Basic layer (overlay) and register security semantics.

The model has the following limitations:

  • No support for polyphase scaling algorithm. Falls back to nearest neighbor when configured to do so.
  • No support for 3D or interlaced video.
  • No support for image enhancing functionality.
  • No colorspace conversion support.
  • No support for two plane YUV memory writeback.

Table 3-199 Ports

Name Protocol Type Description
dc_de_interrupt[2] Signal Master Interrup signalling from display engines.
dc_pvbus_m[2] PVBus Master Bus for processor 0 and 1.
dc_se_interrupt[2] Signal Master Interrupt signalling from scaling engines.
display[2] LCD Master Connection to visualization component.
dp0_clk_in ClockSignal Slave Clock signal for DP0.
dp1_clk_in ClockSignal Slave Clock signal for DP1.
pvbus_s PVBus Slave Slave port for register access.
reset_signal Signal Slave Reset signal.

Table 3-200 Parameters for DP500x2

Name Type Default value Description
disable_snooping_dma bool 0x0 Disable DMA snooping
force_frame_rate int 0x0 If 0 - the input clock is used as PXLCLOCK, if >0 then the model ensures the screen display is refreshed n times per simulated second
Non-ConfidentialPDF file icon PDF version100964_1110_00_en
Copyright © 2014–2020 Arm Limited or its affiliates. All rights reserved.