3.4.38 ARMCortexR5x1CT

ARMCortexR5x1CT CPU component. This model is written in C++ and models version r1p2 of the RTL.

ARMCortexR5x1CT contains the following CADI targets:

  • ARM_Cortex-R5
  • Cluster_ARM_Cortex-R5

ARMCortexR5x1CT contains the following MTI components:

About ARMCortexR5x1CT

  • An ARMCortexR5x2CT component also exists.

  • The per-core parameters are preceded by cpun., where n identifies the core (0 or 1).

  • The allowed values for the LOCK_STEP parameter are:

    0Disable. Set for two independent cores.
    1Lock Step. Appears to the system as two cores but is internally modeled as a single core.
    3Split Lock. Appears to the system as two cores but can be statically configured from reset either as two independent cores or two locked cores. For the model, these are equivalent to Disable and Lock Step, respectively, except for the value of build options registers. The model does not support dynamically splitting and locking the cluster.
  • pvbus_s is the slave port to access the TCM RAM of CPU n. Bits [3:0] of the user flags in the transaction are used to select the TCM:

    • 1 selects the ATCM of CPU 0.
    • 2 selects the BTCM of CPU 0.
    • 3 selects the ATCM of CPU 1.
    • 4 selects the BTCM of CPU 1.
    • Any other value is reserved.

Differences between the model and the RTL

This component has the following differences from the corresponding revision of the RTL implementation:

  • The RR bit in the SCTLR is ignored.
  • The Low Latency Peripheral Port is not modeled.
  • The model only has a single bus master port combining instruction, data, DMA and peripheral accesses. The CP15 control registers associated with peripheral buses preserve values but do not have any other effect.
  • The model only supports static split lock and not dynamic split lock. Contact Arm for details.
  • TCMs are modeled internally and the model does not support external TCMs or the ports associated with them.
  • The model cannot experience an ECC error and does not support fault injection into the system, so Arm does not provide the ability to set error schemes for the caches or TCMs. Contact Arm if you require a particular value in the Build Options registers.

Table 3-174 Ports

Name Protocol Type Description
acp_s PVBus Slave ACP slave port.
cfgatcmsz[2] Value Slave ATCM size.
cfgbtcmsz[2] Value Slave BTCM Size.
cfgend[2] Signal Slave This signal is for EE bit initialisation. This is CFGEE in RTL but cfgend here fastsim consistency reasons.
cfgnmfi[2] Signal Slave Controls non-maskable Fast Interrupts.
clk_in ClockSignal Slave The clock signal connected to the clk_in port is used to determine the rate at which the core executes instructions.
cpuhalt[2] Signal Slave Raising this signal will put the core into halt mode.
event[2] Signal Peer This peer port of event input (and output) is for wakeup from WFE.
fiq[2] Signal Slave This signal drives the CPU's fast-interrupt handling.
groupid Value Slave Group ID used for MPIDR.
initrama[2] Signal Slave If ATCM is enabled at reset.
initramb[2] Signal Slave If BTCM is enabled at reset.
irq[2] Signal Slave This signal drives the CPU's interrupt handling.
loczrama[2] Signal Slave Location of ATCM at reset.
pmuirq[2] Signal Master Interrupt signal from performance monitoring unit.
pvbus_m PVBus Master The core will generate bus requests on this port.
pvbus_s[1] PVBus Slave tcm slave port.
reset[2] Signal Slave Raising this signal will put the core into reset mode.
standbywfe[2] Signal Master This signal indicate if a core is in wfe state RTL calls this WFEPIPESTOPPED.
standbywfi[2] Signal Master This signal indicates if a core is in WFI state RTL uses WFIPIPESTOPPED.
teinit[2] Signal Slave Default exception handling state.
ticks[2] InstructionCount Master This port should be connected to one of the two ticks ports on a 'visualisation' component, in order to display a running instruction count.
vic_ack[2] Signal Master Vic acknowledge port to primary VIC.
vic_addr[2] Value Slave Vic address port from primary VIC.
vinithi[2] Signal Slave This signal controls of the location of the exception vectors at reset.

Table 3-175 Parameters for Cluster_ARM_Cortex-R5

Name Type Default value Description
GROUP_ID int 0x0 Value read in GROUP ID register field, bits[15:8] of the MPIDR
INST_ENDIAN bool 0x1 Controls whether the model supports the instruction endianness bit
LOCK_STEP int 0x0 Affects dual-processor configurations only, and ignored by single-processor configurations
MICRO_SCU bool 0x1 Controls whether the effects of the MicroSCU are modeled
NUM_BREAKPOINTS int 0x3 Controls with how many breakpoint pairs the model has been configured. This only affects the build options registers, because debug is not modeled
NUM_MPU_REGION int 0xc Sets the number of MPU regions
NUM_WATCHPOINTS int 0x2 Controls with how many watchpoint pairs the model has been configured. This only affects the build options registers, because debug is not modeled
SLSPLIT bool 0x0 Sets whether the model starts in split mode or locked mode
cpi_div int 0x1 Divider for calculating CPI (Cycles Per Instruction)
cpi_mul int 0x1 Multiplier for calculating CPI (Cycles Per Instruction)
dcache-state_modelled bool 0x0 Set whether D-cache has stateful implementation
icache-state_modelled bool 0x0 Set whether I-cache has stateful implementation
scheduler_mode int 0x0 Control the interleaving of instructions in this processor. 0, default long quantum. 1, low latency mode, short quantum and signal checking. 2, lock-breaking mode, long quantum with additional context switches near load-exclusive instructions.

Table 3-176 Parameters for ARM_Cortex-R5

Name Type Default value Description
cpu0.CFGATCMSZ int 0xe Sets the size of the ATCM
cpu0.CFGBTCMSZ int 0xe Sets the size of the BTCM
cpu0.CFGEND bool 0x0 Initialize to BE8 endianness
cpu0.CFGIE bool 0x0 Set the reset value of the instruction endian bit
cpu0.CFGNMFI bool 0x0 Enable nonmaskable FIQ interrupts on startup
cpu0.DP_FLOAT bool 0x1 Sets whether double-precision instructions are available
cpu0.INITRAMA bool 0x0 Initialize with TCMA enabled
cpu0.INITRAMB bool 0x0 Initialize with TCMB enabled
cpu0.TEINIT bool 0x0 T32 exception enable. The default has exceptions including reset handled in A32 state
cpu0.VINITHI bool 0x0 Initialize with high vectors enabled
cpu0.atcm_base int 0x40000000 Model-specific. Sets the base address of the ATCM
cpu0.btcm_base int 0x0 Model-specific. Sets the base address of the BTCM
cpu0.dcache-size int 0x10000 Set D-cache size in bytes
cpu0.icache-size int 0x10000 Set I-cache size in bytes
cpu0.min_sync_level int 0x0 Force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
cpu0.semihosting-ARM_HLT int 0xf000 ARM HLT number for semihosting
cpu0.semihosting-ARM_SVC int 0x123456 ARM SVC number for semihosting
cpu0.semihosting-Thumb_HLT int 0x3c Thumb HLT number for semihosting
cpu0.semihosting-Thumb_SVC int 0xab Thumb SVC number for semihosting
cpu0.semihosting-cmd_line string "" Command line available to semihosting SVC calls
cpu0.semihosting-cwd string "" Base directory for semihosting file access.
cpu0.semihosting-enable bool 0x1 Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false
cpu0.semihosting-heap_base int 0x0 Virtual address of heap base
cpu0.semihosting-heap_limit int 0xf000000 Virtual address of top of heap
cpu0.semihosting-hlt-enable bool 0x0 Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true
cpu0.semihosting-stack_base int 0x10000000 Virtual address of base of descending stack
cpu0.semihosting-stack_limit int 0xf000000 Virtual address of stack limit
cpu0.vfp-enable_at_reset bool 0x0 Enable coprocessor access and VFP at reset
cpu0.vfp-present bool 0x1 Set whether model has VFP support
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