3.5.6 DP650

ARM DP650 Display Processor. This model is written in C++.

DP650 contains the following CADI targets:

  • DP650

DP650 contains the following MTI components:

About DP650

This component is a model of the DP650 Display Processor. Connect it to a visualization component to view LCD output. This is the single display configuration of DP650. For the dual display configuration, use DP650x2.

The model has the following limitations:

  • No support for the polyphase scaling algorithm, it always uses nearest neighbor.
  • No support for 3D or interlaced video.
  • No support for image enhancing functionality.
  • No YUV 2-plane support for memory writeback.
  • No color space conversion support.

Table 3-204 Ports

Name Protocol Type Description
clk_in ClockSignal Slave Master clock input, typically 24MHz, to drive pixel clock timing.
display LCD Master Connection to visualization component.
intr Signal Master Interrupt signal.
intr_se Signal Master Interrupt signal from scaling engine.
pvbus_m PVBus Master Bus for processor 0.
pvbus_s PVBus Slave Slave port for register access.
reset_signal Signal Slave Reset signal.
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