3.2.1 MSIRewriter

Recognise writes to the GITS_TRANSLATER register and rewrite them to go to the GITS_TRANSLATE64R register. The DeviceID is expected to be in the bottom 32 bits of ExtendedID of the transaction. Debug transactions and reads are not rewritten. This component can also, optionally, apply a 16 bit 'label' to the top 16 bits of the MasterID in the same way that the Labeller component does. This model is written in LISA+.

MSIRewriter contains the following CADI targets:

  • MSIRewriter

MSIRewriter contains the following MTI components:

Table 3-37 Ports

Name Protocol Type Description
pvbus_m PVBus Master -
pvbus_s PVBus Slave -

Table 3-38 Parameters for MSIRewriter

Name Type Default value Description
GITS_TRANSLATE64R_OFFSET int 0x10048 It is an offset from ITS0-Base.
ITS0-base int 0x0 Register base address for ITS0. This base address is used to recognise writes to the GITS_TRANSLATER register within the ITS0's register frame.
enable_rewriting bool 0x1 Enable rewriting.
label int 0xffffffff If < 2**16 then this is a label that is put in the top 16 bits of MasterID in the same way that the component Labeller does. This labelling is not controlled by enable_rewriting and is performed on all transactions (even rewritten ones)
log int 0x0 Log level, 0 is off.
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