3.9.48 PL310_L2CC

ARM PrimeCell Level 2 Cache Controller (PL310). This model is written in LISA+.

PL310_L2CC contains the following CADI targets:

  • PL310_L2CC

About PL310_L2CC

The presence of additional on-chip secondary cache can improve performance when significant memory traffic is generated by the processor. A secondary cache assumes the existence of a Level 1, or primary, cache that is closely coupled or internal to the processor.

This component has two modes of operation, which are controlled by the cache-state_modelled parameter:

Register view
Cache control registers are present but the cache behavior is not modeled.
Functional model
Cache behavior is modeled.

Arm supports the use of the PL310 when connected to the Arm® Cortex®‑A5 or Cortex‑A9 processor.

This component implements the programmer-visible functionality of the PL310, and excludes some non-programmer visible features. The following features are implemented in the model:

  • Physically addressed and physically tagged.
  • Lockdown format C supported, for data and instructions. Lockdown format C is also known as way locking.
  • Lockdown by line supported.
  • Lockdown by master ID supported.
  • Direct mapped to 16-way associativity, depending on the configuration and the use of lockdown registers. The associativity is configurable as 8 or 16.
  • L2 cache available size can be 16KB to 8MB, depending on configuration and the use of the lockdown registers.
  • Fixed line length of 32 bytes (8 words or 256 bits).
  • Supports all of the AXI cache modes:
    • write-through and write-back.
    • read allocate, write allocate, read and write allocate.
  • Force write-allocate option to always have cacheable writes allocated to L2 cache, for processors not supporting this mode.
  • Normal memory non-cacheable shared reads are treated as cacheable non-allocatable. Normal memory non-cacheable shared writes are treated as cacheable write-through no write-allocate. There is an option, Shared Override, to override this behavior.
  • TrustZone® support, with the following features:
    • Non-Secure (NS) tag bit added in tag RAM and used for lookup in the same way as an address bit.
    • NS bit in Tag RAM used to determine security level of evictions to L3.
    • Restrictions for NS accesses for control, configuration, and maintenance registers to restrict access to secure data.
  • Pseudo-Random victim selection policy. You can make this deterministic with use of lockdown registers.
  • Software option to enable exclusive cache configuration.
  • Configuration registers accessible using address decoding in the component.
  • Interrupt triggering in case of an error response when accessing L3.
  • Maintenance operations.
  • Prefetching capability.

The performance of this component depends on the configuration of the associated L1 caches and the mode it is in:

  • Register mode: no significant effect.
  • Functional mode with functional-mode L1: the addition of a functional L2 cache has minimal further impact on performance when running applications that are cache-bound.
  • Functional mode with a register-mode L1: there is a significant impact on system performance.

Differences between the model and the RTL

This model does not implement the following features, most of which are not relevant from a PV modeling point of view:

  • There is no interface to the data and tag RAM as they are embedded to the model.
  • Critical word first linefill is not supported, as it is not relevant for PV modeling.
  • Buffers are not modeled.
  • Outstanding accesses on slave and master ports cannot occur by design in a PV model as all transactions are atomic.
  • Option to select one or two master ports and option to select one or two slave ports is not supported. Only one master port and one slave port is supported.
  • Clock management and power modes are not supported, as they are not relevant for PV modeling.
  • Wait, latency, clock enable, parity, and error support for data and tag RAMs not included, as they are not relevant for PV modeling, and the data and tag RAMs embedded in the model cannot generate error responses.
  • MBIST support is not included.
  • Debug mode and debug registers are not supported.
  • Test mode and scan chains are not supported.
  • L2 cache event monitoring is not supported.
  • Address filtering in the master ports is not supported.
  • Performance counters are not supported.
  • Specific Cortex‑A9 related optimizations are not supported: Prefetch hints, Full line of zero and Early write response.
  • Hazard detection is not required because of the atomic nature of the accesses at PV modeling and the fact that buffers are not modeled, therefore hazards cannot occur.
  • Registers that belong to unimplemented features are accessible but do not have any functionality.

This model implements the following features differently to the hardware:

  • Error handling. DECERR from the master port is mapped to SLVERR. Internal errors in cache RAM (like parity errors) cannot happen in the model.
  • Background cache operations do not occur in the background. They occur atomically.
  • The LOCKDOWN_BY_LINE and LOCKDOWN_BY_MASTER parameter values are reflected in the CacheType register, but the feature is not switched off when the parameter is 0.

This feature is additional:

  • Data RAM and Tag RAM are embedded to the model.

Table 3-382 Ports

Name Protocol Type Description
DECERRINTR Signal Master Decode error received on master port from L3.
ECNTRINTR Signal Master Event Counter Overflow / Increment.
ERRRDINTR Signal Master Error on L2 data RAM read.
ERRRTINTR Signal Master Error on L2 tag RAM read.
ERRWDINTR Signal Master Error on L2 data RAM write.
ERRWTINTR Signal Master Error on L2 tag RAM write.
L2CCINTR Signal Master Combined interrupt output.
PARRDINTR Signal Master Parity error on L2 data RAM read.
PARRTINTR Signal Master Parity error on L2 tag RAM read.
SLVERRINTR Signal Master Slave error on master port from L3.
pvbus_m PVBus Master Master port for connection to PV bus master/decoder.
pvbus_s PVBus Slave Slave port for connection to PV bus master/decoder.

Table 3-383 Parameters for PL310_L2CC

Name Type Default value Description
ASSOCIATIVITY int 0x0 Associativity for Auxiliary Control Register
CACHEID int 0x0 Cache controller cache ID
CFGBIGEND int 0x0 Big-endian mode for accessing configuration registers out of reset
LOCKDOWN_BY_LINE int 0x0 Lockdown by line - value is reflected in CacheType register Bit 25, but the feature is not switched off when the parameter is 0
LOCKDOWN_BY_MASTER int 0x0 Lockdown by master - value is reflected in CacheType register Bit 26, but the feature is not switched off when the parameter is 0
REGFILEBASE int 0x1f002000 Base address for accessing configuration registers
WAYSIZE int 0x1 Size of ways for Auxiliary Control Register
cache-state_modelled bool 0x0 Specifies whether real cache state is modelled (vs. register model)
delay_cache_hit int 0x0 Cost to handle a cache hit
delay_cache_miss int 0x0 Cost to handle a cache miss
delay_cache_perbeat int 0x0 Cost to handle one beat of cache data movement
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