7.2.2 BasePlatformPCIRevC component

This component is an integrated PCIe subsystem which forms part of the Base Platform RevC. It incorporates an SMMUv3, a PCIe, an AHCI controller, and two PCI devices which wrap a pair of virtio PCI block devices. This model is written in LISA+.


  • You can include this component in a platform model, but Arm does not support using its subcomponents to create your own PCIe platform.
  • The PCIe is not an implementation of any specific IP, but a functional, and limited, implementation of the PCIe standard.

BasePlatformPCIRevC is composed of the following model components:


The bridge from the Programmer's View bus to the PCI bus.


A wrapper around the underlying virtio block device. There are two block devices in the system, 0 and 1.


The instances of the virtio block device component.


An AHCI_SATA component with the following features:

  • Each AHCI controller supports up to 32 simulated SATA disks. The configuration parameter image_path is a comma-separated list of one or more disk images.
  • Supports 64-bit addresses.
  • Supports plain, linear disk images, but also works with sparse files.

Some interesting options are:

  • If the following options are set to non-zero values, they print messages about the operation of the bridge. The higher the value, the more verbose the component is:

    pci.pvbus2pci.diagnostics=0x0    # (int) default = '0x0': Diagnostics level: [0x0..0x4]
    pci.pcidevice<N>.diagnostics=0x0 # (int) default = '0x0': Diagnostics level: [0x0..0x4]
  • Each PCI device uses three BARs; one for config space, one for the MSI-X table structure and one for the MSI-X Pending Bit Array. Each of these can be configured to be 32 bits or 64 bits wide.

    The Bus and Device number can be configured for each PCI device. If the device advertises MSI-X, support can be configured.

    pci.pcidevice<N>.bus=0x0        # (int ) default = '0x0' : Bus number for this device : [0x0..0xFF]
    pci.pcidevice<N>.device=0x0     # (int ) default = '0x0' : Device number on this bus : [0x0..0x1F]
    pci.pcidevice<N>.bar0_64bit=0   # (bool) default = '0' : If BAR 0 is 64 bits wide, if region size is nonzero
    pci.pcidevice<N>.msix_support=0 # (bool) default = '0' : Enable device support for MSI-X
    pci.pcidevice<N>.bar2_64bit=0   # (bool) default = '0' : If BAR 2 is 64 bits wide, if region size is nonzero
    pci.pcidevice<N>.bar4_64bit=0   # (bool) default = '0' : If BAR 4 is 64 bits wide, if region size is nonzero
  • The following option configures the image file that the virtio block device exposes:

    pci.pcivirtioblockdevice<N>.image_path="" # (string) default = '' : image file path
  • There are two PVBusLoggers in the pvbus2pci component. One is in front of the Configuration space and one is in front of the Device space:

  • There is one PVBusLogger in the pcidevice component. This reports on DMA accesses by the PCI device:

  • There is a PVBusLogger downstream of the SMMU. This reports on the transactions after they have been transformed by the SMMU:


    For example, you can see all accesses to device space by adding the following options to the command line:

    --plugin GenericTrace.so
    -C TRACE.GenericTrace.trace-sources="FVP_Base_AEMv8A_AEMv8A-PCI.pci.pvbus2pci.devicelogger.*"
  • To supply the AHCI controller with one or more SATA disk images, use the image_path parameter. For example:

    -C pci.ahci_pci.ahci.image_path=disk1tb.img,disk8tb.img

Table 7-1 BasePlatformPCIRevC ports

Name Protocol Type Description
pvbus_address_map_s PVBus Slave Input port to service transactions based on the PVBus protocol.
pvbus_address_map_m PVBus Master Output port to send out PVBus transactions that are not handled by this component.
system_reset Signal Slave Input port to handle reset signals. It is used to reset the internal state of this component.
sev_out Signal Peer Port to send out a notification of the occurrence of an event as sg::Signal to a peer.
interrupts[224] Signal Master Array of output ports of type sg::Signal to send out interrupts generated by this component.
pvbus_pci_dma_m PVBus Master Output port to send out any DMA (of PVBus protocol) accesses originating from this component.
clk_in ClockSignal Slave Input port to connect to a ClockSignal provider.

Table 7-2 BasePlatformPCIRevC parameters

Name Type Allowed values Default value Description
ITS0-base uint64_t 0-0xFFFFffffFFFFffff 0x2f020000 The ITS0 Base address.
pci_smmuv3.mmu.SMMU_IDR1 uint32_t 0-0xFFFFffff 0xe739d10 SMMU_IDR1.
pci_smmuv3.mmu.smmu_msi_device_id uint32_t 0-0xFFFFffff 0x10000

When appropriately enabled, assume that MSIs that are generated by the SMMU are presented to the GIC with this DeviceID.

See parameter msi_attribute_transform and enable_device_id_checks.

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