3.7.37 VirtioPCIBlockDevice

virtio block device with PCI transport. This model is written in C++.

VirtioPCIBlockDevice contains the following CADI targets:

  • VirtioPCIBlockDevice

VirtioPCIBlockDevice contains the following MTI components:

Table 3-270 Ports

Name Protocol Type Description
info_s Value_64 Slave Communicates PCI Info values to device.
intr Signal Master Virtio device sets interrupt to signal completion.
msixintr[2] Signal Master Interrupts for MSI-X table entries.
pvbus PVBus Slave Virtio pci/control/config/status registers.
virtio_m PVBus Master Virtio device performs DMA accesses via master.
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