3.7.18 MemoryMappedGenericWatchdog

ARM Generic Watchdog. This model is written in LISA+.

MemoryMappedGenericWatchdog contains the following CADI targets:

  • MemoryMappedGenericWatchdog

MemoryMappedGenericWatchdog contains the following MTI components:

About MemoryMappedGenericWatchdog

This is a high-level watchdog that generates two interrupts rather than an interrupt followed by a reset.

Table 3-244 Ports

Name Protocol Type Description
WS0 Signal Master Set when watchdog expired for the first time.
WS1 Signal Master Set when watchdog expired for the second time.
cntvalueb CounterInterface Slave For connection to MemoryMappedCounterModule.
ctl_pvbus_s PVBus Slave Access to control frame.
ref_pvbus_s PVBus Slave Access to refresh frame.
reset_in Signal Slave Reset.

Table 3-245 Parameters for MemoryMappedGenericWatchdog

Name Type Default value Description
NONSECURE bool 0x0 Non-Secure
diagnostics int 0x0 Diagnostics
product_id int 0x0 Product Identifier
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