3.4.36 ARMCortexM55CT

CortexM55CT CPU component. This model is written in C++.

ARMCortexM55CT contains the following CADI targets:

  • ARM_Cortex-M55

ARMCortexM55CT contains the following MTI components:

Differences between the CT model and the RTL

The CT model does not support the following functionality:

  • Cross Trigger Interface (CTI).
  • Programmable MBIST controller (PMC-100).
  • Error Correcting Code (ECC).
  • Q-Channel.

The following interfaces and registers are not modeled:

  • ITM and ETM trace and trace synchronization and trigger interface signals.
  • Dual-core lock-step operation.
  • Interrupt latencies.
  • Memory System Control Register (MSCR).
  • Prefetcher Control Register (PFCR).
  • Direct cache access registers.

Differences between the FVP_MPS2 model and the MPS2 specification

  • The model does not have the random number generator or unique ID/secure storage mentioned in the MPS2 specification because the programmer's view of these devices is yet to be defined.
  • The Ethernet controller in the model is a LAN91C111. The MPS2 documents, including those for pre-v8-M cores, specify a LAN9220.
  • MTB, ETM, and TPIU are not supported. MTB RAM is absent.
  • In the Memory Gating Unit, the model provides a configurable block size. For performance reasons, the minimum block size in the model is 4096 bytes. Hardware and later models might allow smaller block sizes. Software should always use the BLK_CFG register to determine block size.
  • As in previous MPS2 Fast Models, some of the peripherals have minimal implementations:
    • The Audio controller is RAZ/WI.
    • Only the touchscreen functionality of the STMPE811 touchscreen controller is implemented.
    • A subset of the Ampire LCD module's graphics modes are supported.
  • The usual general Fast Models restrictions apply.

Implementation of ITM in M-class models

This model has a parameter that enables partial support for Instrumentation Trace Macrocell (ITM). In hardware or RTL, trace data from ITM is sent in packets to the trace block serially using a single pin or wire. In the model, if it is enabled, the ITM trace data is output using an MTI trace source called ITM. The ITM trace source has an ITM_PACKET_TYPE field. The following table shows which packet types the model supports:

Table 3-169 ITM_PACKET_TYPE field values that the model supports

Field value Description Supported by model
ITM_SYNC Synchronization packet Not supported.
ITM_P_OVERFLOW Protocol: Overflow packet Not supported.
ITM_P_LOCAL_TIMESTAMP Protocol: Local timestamp packets Not supported.
ITM_P_GLOBAL_TIMESTAMP Protocol: Global timestamp packets Not supported.
ITM_P_EXTEN Protocol: Extension packet Not supported.
ITM_S_INSTRUMENTATION Source: Instrumentation packet Supported.
ITM_S_DWT_EVENT_COUNTER Hardware source: Event counter wrapping Not supported.
ITM_S_DWT_EXCEPTION Hardware source: Exception tracing Supported.
ITM_S_DWT_PC_SAMPLING Hardware source: PC sampling Not supported.
ITM_S_DWT_DATA_PC_TRACE Hardware source: DWT Data trace PC value Supported.
ITM_S_DWT_DATA_ADDRESS_TRACE Hardware source: DWT Data trace address value Supported.
ITM_S_DWT_DATA_DATA_TRACE Hardware source: DWT Data trace DATA value Supported.

Table 3-170 Ports

Name Protocol Type Description
ahbd PVBus Slave -
ahbp_m PVBus Master The core will generate Vendor System data accesses on this port.
auxfault Value Slave This is wired to the Auxiliary Fault Status Register.
bigend Signal Slave Configure big endian data format.
clk_in ClockSignal Slave The clock signal connected to the clk_in port is used to determine the rate at which the core executes instructions. Referred to in some documents as 'CLKIN'.
coproc_bus CoprocBusProtocol Slave Co-Processor Interface
cpuwait Signal Slave Stall the CPU out of reset
currns Signal Master Current Security state of the processor
currpri Value Master Current execution priority.
dbgen Signal Slave Invasive debug enable
dbgrestart Signal Slave Request for synchronised exit from halt mode
dbgrestarted Signal Master Handshakes with DBGRESTART
edbgrq Signal Slave External request to enter halt mode
event Signal Peer This peer port of event input (and output) is for wakeup from WFE and corresponds to the RTL TXEV and RXEV signals.
fpxxc Value Master Port which sends the value of the FPXXC cumulative exception flags.
halted Signal Master Indicates that the processor is in halt mode
idau PVBus Master The core will generate IDAU requests on this port.
idau_invalidate_region Value_64 Slave 64 bit number to invalid IDAU memory ranage (start_address<<32|end_address)
initnsvtor Value Slave Reset configuration port - Non-Secure Vector table offset (VTOR.TBLOFF[31:7]) out of reset This port remains functional no matter ARMv8-M Security Extensions are included or not When ARMv8-M Security Extensions are not included, all exceptions will use NS vector base address given by this port.
initpahben Signal Slave Enable P-AHB on the next reset
initsvtor Value Slave Reset configuration port - Secure Vector table offset (VTOR.TBLOFF[31:7]) out of reset It becomes functional when ARMv8-M Security Extensions are included When ARMv8-M Security Extensions are not included, this port will be ignored.
inittcmen[2] Signal Slave Reset configuration port - TCM enable initialisation out of reset Bit[0] HIGH = ITCM is enabled Bit[1] HIGH = DTCM is enabled
intnum Value Master Exception number of the current execution context (from IPSR[8:0]) When the processor is in Thread mode, INTNUM is 0 When the processor is in Handler mode, INTNUM is the exception number of the currently-executing exception.
irq[480] Signal Slave This signal array delivers signals to the NVIC.
locknsmpu Signal Slave Disable writes to the Non-Secure MPU_*_NS registers
locknsvtor Signal Slave Cortex-M55-specific LOCKNSVTOR, LOCKSVTAIRCR, LOCKSMPU, LOCKNSMPU, LOCKSAU. Disable writes to VTOR_NS
lockpahb Signal Slave P-AHB related ports Disable writes to PAHBCR
locksau Signal Slave Disable writes to the SAU_* registers
locksmpu Signal Slave Disable writes to the Secure MPU_* registers
locksvtaircr Signal Slave Disable writes to VTOR_S, AIRCR.PRIS, AIRCR.BFHFNMINS
lockup Signal Master Asserted when the processor is in lockup state.
niden Signal Slave Non-invasive debug enable
nmi Signal Slave Configure non maskable interrupt.
poreset Signal Slave Raising this signal will do a power-on reset of the core.
prequest PChannel Slave Low Power Interface
pv_ppbus_m PVBus Master The core will generate External Private Peripheral Bus requests on this port.
pvbus_m PVBus Master The core will generate bus requests on this port.
qrequest PChannel Slave -
sleepdeep Signal Master Asserted when the processor is in deep sleep.
sleeping Signal Master Asserted when the processor is in sleep.
spiden Signal Slave Secure invasive debug enable
spniden Signal Slave Secure non-invasive debug enable
stcalib[2] Value Slave This is the calibration value for the SysTick timer.
stclk ClockSignal Slave This is the reference clock for the SysTick timer.
sysreset Signal Slave Raising this signal will put the core into reset mode (but does not reset the debug logic).
sysresetreq Signal Master Asserted to indicate that a reset is required.
ticks InstructionCount Master Port allowing the number of instructions since startup to be read from the CPU.
wicenack Signal Master Acknowledge signal for WICENREQ
wicenreq Signal Slave Request for deep sleep to be WIC-based deep sleep.
wicsense[483] Signal Master Indicates which input events can cause the WIC to generate the WAKEUP signal.

Table 3-171 Parameters for ARM_Cortex-M55

Name Type Default value Description
BEATS_PER_TICK int 0x2 Number of beats from each in-flight vector instruction executed in 1 tick (1,2 or 4).
BF_is_nop bool 0x0 BF instruction executes as NOP, even if we have LO_BRANCH_INFO.
CFGBIGEND bool 0x0 Initialize processor to big endian mode
CFGDTCMSZ int 0x9 Size of the data TCM. 0=No DTCM implemented. Otherwise=Size of DTCM=pow(2, CFGDTCMSZ - 1) KB. Minimum size is 4KB
CFGITCMSZ int 0x9 Size of the instruction TCM. 0=No ITCM implemented. Otherwise=Size of ITCM=pow(2, CFGITCMSZ - 1) KB. Minimum size is 4KB
CFGMEMALIAS int 0x0 Memory address alias bit for the ITCM, DTCM and P-AHB regions. 0=No alias, 1=Alias bit 24, 2=Alias bit 25, 4=Alias bit 26, 8=Alias bit 27, 16=Alias bit 28
CFGPAHBSZ int 0x0 Size of the P-AHB peripheral port memory region. 0=P-AHB disabled, 1=64MB, 2=128MB, 3=256MB, 4=512MB
CPIF bool 0x1 Specifies whether the external coprocessor interface is included
CPNSPRESENT int 0xff Bit N means external coprocessor N (CP7:CP0) is accessible in Non-Secure state
CPSPRESENT int 0xff Bit N means external coprocessor N (CP7:CP0) is accessible in Secure state
DBGLVL int 0x2 0: Minimal debug; 1: 2 Watchpoints, 4 Breakpoint comparators; 2: 4 Watchpoints, 8 Breakpoint comparators
DCACHESZ int 0xf Whether the D-cache is included and, if included, the size of it. Bit 0: 0=No D-cache included, 1=D-cache included. Bits [4:1]: 0x0=4KB D-cache, 0x1=8KB D-cache, 0x3=16KB D-cache, 0x7=32KB D-cache, 0x15=64KB D-cache
DTGU bool 0x0 DTCM Security Gate Unit included
DTGUBLKSZ int 0x3 DTCM gate unit block size. Size=pow(2, DTGUBLKSZ + 5) bytes
DTGUMAXBLKS int 0x0 Maxiumum number of DTCM gate unit blocks. Number of blocks=pow(2, DTGUMAXBLKS)
ECOREVNUM int 0x0 ECO Revision number
ERRDEVID.NUM int 0x38 RAS: Number of implemented error record indexes, 0 to 56.
ETM bool 0x1 Support for ETM trace. false : No ETM trace included, true: ETM trace included
FPU bool 0x1 Set whether the model has VFP support
ICACHESZ int 0xf Whether the I-cache is included and, if included, the size of it. Bit 0: 0=No I-cache included, 1=I-cache included. Bits [4:1]: 0x0=4KB I-cache, 0x1=8KB I-cache, 0x3=16KB I-cache, 0x7=32KB I-cache, 0x15=64KB I-cache
ID_ISAR0.CmpBranch int 0x3 Support for Compare and Branch instructions. 1 = Supports CBNZ and CBZ instructions; 3 = Supports non-predicated low overhead looping (WLS, DLS, LE, and LC) and branch future (BF, BFX, BFL, BFLX, and BFCSEL) instructions.
INITNSVTOR int 0x0 Non-Secure vector-table offset at reset
INITPAHBEN bool 0x0 The P-AHB enable state at reset
INITSVTOR int 0x0 Secure vector-table offset at reset
IRQDIS0 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+0]
IRQDIS1 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+32]
IRQDIS10 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+320]
IRQDIS11 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+352]
IRQDIS12 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+384]
IRQDIS13 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+416]
IRQDIS14 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+448]
IRQDIS2 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+64]
IRQDIS3 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+96]
IRQDIS4 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+128]
IRQDIS5 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+160]
IRQDIS6 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+192]
IRQDIS7 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+224]
IRQDIS8 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+256]
IRQDIS9 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+288]
IRQLVL int 0x3 Number of bits of interrupt priority
ITGU bool 0x0 ITCM Security Gate Unit included
ITGUBLKSZ int 0x3 ITCM gate unit block size. Size=pow(2, ITGUBLKSZ + 5) bytes
ITGUMAXBLKS int 0x0 Maxiumum number of ITCM gate unit blocks. Number of blocks=pow(2, ITGUMAXBLKS)
ITM bool 0x1 Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included
IWIC bool 0x1 Include support for Internal Wake-up Interrupt Controller
LOCKDTGU bool 0x0 Lock down of Data TGU registers write
LOCKITGU bool 0x0 Lock down of Instruction TGU registers write
LOCKTCM bool 0x0 Lock down of TCM registers write
LOCK_NS_MPU bool 0x0 Lock down of Non-Secure MPU registers write
LOCK_SAU bool 0x0 Lock down of SAU registers write
LOCK_S_MPU bool 0x0 Lock down of Secure MPU registers write
MPU_NS int 0x8 Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions
MPU_S int 0x8 Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored
MVE int 0x1 Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included
NUMIRQ int 0x20 Number of user interrupts
SAU int 0x4 Number of SAU regions (0 => no SAU)
SECEXT bool 0x1 Whether the ARMv8-M Security Extensions are included
WICLINES int 0x23 Number of lines supported by the WIC interface
aircr_iesb_is_writable bool 0x1 IS the AIRCR.IESB bit [5] writable?
aircr_iesb_reset bool 0x0 Set the AIRCR.IESB bit [5] after reset
cde_impl_name string "" Name of the CDE implementation for this core (implementation contributed by MTI plugin).
cde_plugin_path string "" Path for plugin implementing prototype interface for CDE instructions.
cpi_div int 0x1 divider for calculating CPI (Cycles Per Instruction)
cpi_mul int 0x1 multiplier for calculating CPI (Cycles Per Instruction)
dcache-state_modelled bool 0x0 Set whether D-cache has stateful implementation
dcache-ways int 0x4 L1 D-cache ways (sets are implicit from size)
delay_sysreg_update bool 0x0 Delay Sys Reg (fault mask) update to contextSync
duplicate_CADI_TCM_writes bool 0x0 CADI writes to TCMs are also sent to downstream memory at same addresses (for validation platforms)
execute_via_archex bool 0x1 Use ArchEx-generated code from V8_1_PRE_EAC04_AUGUST_RELEASE for execution
has_cde bool 0x0 Enables Custom Datapath Extensions
has_pmu bool 0x0 Availability of optional PMU.
has_unpriviledged_debug bool 0x1 Unpriviledged Debug Extension supported for Mainline Extension
icache-state_modelled bool 0x0 Set whether I-cache has stateful implementation
icache-ways int 0x2 L1 I-cache ways (sets are implicit from size)
master_id int 0x0 Master ID presented in bus transactions
min_sync_level int 0x0 force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
mve_unpred_config_json string "'[["CLEAR_IT","VPNOT_T1","InITBlock"],["OK","VMINNMV_f_T2","Rda==11x1"],["OK","VDDUP","curOffset MOD imm32 != 0"],["OK","VDDUP","bufSize MOD imm32 != 0"],["OK","VDDUP","curOffset >= bufSize "]]'" A JSON array of arrays of the form [unpred_result, instr, cond] forunpredictable configruation for MVE. Either instr or cond may be omitted. The first match wins. Use 'list' to show the available options
num_pmu_counters int 0x1f Number of available PMU counters.
ras_ERRFR0 string "'{"ED":0x1,"UE":0x1}'" A JSON object or array of objects for each field of ERRFR. Records not described default to RAZ e.g. '{"ED":0x1,"UE":0x1}'.
ras_cei_pin int 0x2 RAS: Critical error interrupt pin.
ras_cei_support bool 0x1 RAS: Whether Critical Error Interrupt is supported
ras_eri_pin int 0x1 RAS: Error recovery interrupt pin.
ras_eri_support bool 0x1 RAS: Whether Error Recovery Interrupt is supported
ras_error_record int 0xffffffffffffff 56 bit value that specifies which nodes out of 0-55 are implemented (ERRDEVID is derived from this parameter)
ras_fhi_pin int 0x0 RAS: Fault handling interrupt pin.
ras_fhi_support bool 0x1 RAS: Whether Fault Handling Interrupt is supported
scheduler_mode int 0x0 Control the interleaving of instructions in this processor (0=default long quantum, 1=low latency mode, short quantum and signal checking, 2=lock-breaking mode, long quantum with additional context switches near load-exclusive instructions, 3=ISSCompare)
semihosting-Thumb_SVC int 0xab T32 SVC number for semihosting
semihosting-cmd_line string "" Command line available to semihosting SVC calls
semihosting-cwd string "" Base directory for semihosting file access.
semihosting-enable bool 0x1 Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
semihosting-heap_base int 0x0 Virtual address of heap base
semihosting-heap_limit int 0x10700000 Virtual address of top of heap
semihosting-prefix bool 0x0 Prefix semihosting output with target instance name
semihosting-stack_base int 0x10700000 Virtual address of base of descending stack
semihosting-stack_limit int 0x10800000 Virtual address of stack limit
trace_style int 0x0 MVE instruction trace style: 0=Tarmac-like from instDB.json, 1=execute function+params (for debug), 2 = Rosetta. Add 16 for [**--] beat trace. Add 32 for tracing IMPLIED LOB instructions. Add 64 to change opcode of implied BF to 0xBF00
unpred_config_json_file string "" Path to the unpredictable configuration file in JSON format
vfp-enable_at_reset bool 0x0 Enable VFP in CPACR, CPPWR, NSACR at reset. Warning: Arm recommends going through the implementation's suggested VFP power-up sequence!
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