3.9.47 PL192_VIC

ARM PrimeCell Vectored Interrupt Controller(PL192). This model is written in LISA+.

PL192_VIC contains the following CADI targets:

  • PL192_VIC

PL192_VIC contains the following MTI components:

About PL192_VIC

This component aggregates interrupts and generates interrupt signals for the Arm® processor. When coupled with an Arm processor that provides a VIC port, routing to the appropriate interrupt handler can optionally be performed in hardware, reducing interrupt latency. The PL192_VIC can also be daisy-chained with other PL192 VICs to permit more than 32 interrupts. The VIC supports hardware and software prioritization of interrupts.

Table 3-381 Ports

Name Protocol Type Description
VICIRQACK Signal Slave Receive acknowledge signal from next level VIC or processor.
VICIRQACKOUT Signal Master Used to send out acknowledge signals when daisy chained.
VICIntSource[32] Signal Slave Interrupt source input sources.
VICVECTADDRIN ValueState Slave Used to receive vector address when daisy chained.
VICVECTADDROUT ValueState Master Used to send vector address to next level VIC or processor.
nVICFIQ Signal Master Send out FIQ signal to the next level VIC or CPI.
nVICFIQIN Signal Slave Used to receive FIQ signal when daisy chained.
nVICIRQ Signal Master Send out IRQ signal to the next level VIC or procesessor.
nVICIRQIN Signal Slave Used to receive IRQ signal when daisy chained.
pvbus PVBus Slave Slave port for register access.
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