3.7.17 MemoryMappedGenericTimer

ARM Generic Timer. This model is written in LISA+.

MemoryMappedGenericTimer contains the following CADI targets:

  • MemoryMappedGenericTimer

MemoryMappedGenericTimer contains the following MTI components:

Table 3-242 Ports

Name Protocol Type Description
cntpsirq[8] Signal Master -
cntvalueb CounterInterface Slave For connection to MemoryMappedCounterModule.
pvbus_base_s[8] PVBus Slave -
pvbus_ctlbase_s PVBus Slave -
pvbus_el0base_s[8] PVBus Slave -
timer_reset Signal Slave Reset.

Table 3-243 Parameters for MemoryMappedGenericTimer

Name Type Default value Description
bypass_ctlbase bool 0x0 Bypass CNTBase Access Control. Enable if only timer frame feature is required without CNTBase access control
cntel0acr_implemented int 0x0 A bit-field of 8 bits, where bit {n} enables CNTEL0ACR for timer frame {n}
diagnostics int 0x0 Diagnostics
frame_security string "" Hard-wired/configurable security for frames (N/S/X, one character per timer frame)
num_timers int 0x1 Number of timer frames
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