3.9.59 SMSC_91C111

10/100 Non-PCI Ethernet Controller(SMSC 91C111). This model is written in C++.

SMSC_91C111 contains the following CADI targets:

  • SMSC_91C111

SMSC_91C111 contains the following MTI components:

About SMSC_91C111

This component provides the register interface of the SMSC part and can be configured to act as an unconnected Ethernet port, or an Ethernet port connected to the host by an Ethernet bridge.

It uses a banked register model of primarily 16-bit registers. There are also indirectly accessible registers for the PHY unit.

If a MAC address is not specified in the mac_address parameter, the simulator takes the default MAC address, which is randomly generated. This provides some degree of MAC address uniqueness when running models on multiple hosts on a local network.


DHCP servers allocate the IP addresses, but because they sometimes do this based on the MAC address provided to them, using random MAC addresses might interact unfortunately with some DHCP servers.

Table 3-403 Ports

Name Protocol Type Description
clock ClockSignal Slave Clock input, typically 25MHz, which sets the master transmit/receive rate.
eth VirtualEthernet Master Ethernet port.
intr Signal Master Interrupt signal.
pvbus PVBus Slave Slave port for register access.
state ValueState_64 Master State port to retrieve state of host bridge
Non-ConfidentialPDF file icon PDF version100964_1110_00_en
Copyright © 2014–2020 Arm Limited or its affiliates. All rights reserved.