5.13.1 ScalableVectorExtension parameters

This section describes the parameters for the ScalableVectorExtension plug-in.

Each parameter is prefixed with SVE.ScalableVectorExtension, for example:


Table 5-14 ScalableVectorExtension parameters

Name Type Default value Runtime Description
clear_constrained_lanes int 0x0 false When a constrained vector length increases, previously inaccessible bits are set to zero according to the value of this parameter. Possible values are:
0x2If the register was written to while the vector length was constrained.
combine_movprfx_and_destructive bool false false Attempt to combine the execution of MOVPRFX and the destructively encoded instruction that follows it.
disable_speculative_accesses bool false false All speculative memory accesses behave as though faulting without accessing memory.
disass_internal bool false false Use the generated disassembler, which produces lower quality disassembly but always matches the instruction decoder.
enable_at_reset bool false false Start with system registers set up for Scalable Vector Extension use.
ffr_16b_pattern_UNKNOWN int 0x0 false A specific 16-bit unknown value that is used by parameter force_UNKNOWN_to_ffr.
force_UNKNOWN_to_ffr bool false false If WRFFR, writes a non-monotonic value to FFR. Enabling this parameter overwrites FFR with a specific 16-bit unknown value. See ffr_16b_pattern_UNKNOWN.
fp_exception_report_lowest bool false false If true, for multiple trapped FP exceptions, report the lowest lane in VECITR. Otherwise, report the highest.
fp_exception_set_tfv bool true false Set ESR_ELx.TFV during FP exception. Trapped exception flags are valid.
fp_exception_set_vecitr bool false false If true, set ESR_ELx.VECITR during FP exception. Otherwise, set RES0.
has_sve2 bool true false Whether SVE2 is implemented.
has_sve2_aes int 0x2 false Whether SVE2 AES instructions are implemented. Possible values are:
0x0Not implemented.
0x1SVE2 AESE, AESD, AESMC, and AESIMC are implemented.
0x2Same as 1, but in addition, SVE2 PMULLB and PMULLT with 64-bit source are implemented.
has_sve2_bit_perm bool true false Whether SVE2 BitPerm instructions are implemented.
has_sve2_sha3 bool true false Whether SVE2 SHA3 instructions are implemented.
has_sve2_sm4 bool true false Whether SVE2 SM4 instructions are implemented.
support_npot_vl bool true false Whether vector lengths that are not a power of two are supported.
undef_invalid_combined_movprfx bool true false If a combined MOVPRFX is invalid, raise an UNDEF exception. Otherwise NOP the second half of the register.
unknown_value int 0xdeaddeaddeaddead false Simulated value for a state that has an unknown value after reset.
veclen int 0x8 false Size of the vector in units of 64-bit blocks. Allowed range is 0x2-0x20.
Non-ConfidentialPDF file icon PDF version100964_1110_00_en
Copyright © 2014–2020 Arm Limited or its affiliates. All rights reserved.