3.9.37 PL022_SSP

ARM PrimeCell Synchronous Serial Port(PL022). This model is written in LISA+.

PL022_SSP contains the following CADI targets:

  • ClockDivider
  • PL022_SSP

PL022_SSP contains the following MTI components:

Differences between the model and the RTL

Although the PL022_SSP component has clock input, it is not internally clock-driven. This is different to the hardware.


This component is a preliminary release. It is not a fully-supported peripheral.

Table 3-362 Ports

Name Protocol Type Description
clk ClockSignal Slave Main PrimeCell SSP clock input.
clkin ClockSignal Slave PrimeCell SSP clock input.
clkout ClockSignal Master Clock output.
intr Signal Master Interrupt signaling.
pvbus PVBus Slave Slave port for connection to PV bus master/decoder.
rorintr Signal Master Receive overrun interrupt.
rtintr Signal Master Receive timeout interrupt. We don't implement time out interrupt.
rx_dma_port PL080_DMAC_DmaPortProtocol Master PrimeCell SSP receive DMA port.
rxd Value Slave PrimeCell SSP receive data.
rxintr Signal Master Receive FIFO service request port.
tx_dma_port PL080_DMAC_DmaPortProtocol Master PrimeCell SSP transmit DMA port.
txd Value Master PrimeCell SSP transmit data.
txintr Signal Master Transmit FIFO service request.
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