3.5.2 DP500

ARM DP500 Display Processor. This model is written in C++.

DP500 contains the following CADI targets:

  • DP500

DP500 contains the following MTI components:

About DP500

This model has basic support for the display and scaling engines. Connect it to a visualization component to view LCD output. This is the single display configuration of DP500. For the dual display configuration, use DP500x2.

It passes tests as part of a booting Android kernel and running under the control of the official DP500 drivers.

It provides the following functionality:

  • All RGB and YUV format parsing.
  • Color adjustment in Display Engine (DE).
  • Nearest neighbor scaling.
  • All layers.
  • Alpha blending.
  • Memory writeback.
  • Inverse gamma adjustment.
  • Basic layer (overlay) and register security semantics.

The model has the following limitations:

  • No support for polyphase scaling algorithm. Falls back to nearest neighbor when configured to do so.
  • No support for 3D or interlaced video.
  • No support for image enhancing functionality.
  • No colorspace conversion support.
  • No support for two plane YUV memory writeback.

Table 3-198 Ports

Name Protocol Type Description
clk_in ClockSignal Slave Master clock input, typically 24MHz, to drive pixel clock timing.
display LCD Master Connection to visualization component.
intr Signal Master Interrupt signal.
intr_se Signal Master Interrupt signal from scaling engine.
pvbus_m PVBus Master Bus for processor 0.
pvbus_s PVBus Slave Slave port for register access.
reset_signal Signal Slave Reset signal.
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