1.4.6 Memory access in PV models

This section describes the kinds of memory access in PV models.

About memory access in PV models

PV models use a PVBusMaster subcomponent to communicate with slaves in a System Canvas generated system. This provides efficient access to memory-like slaves and relatively efficient access to device-like slaves.

Memory access in PV models differs from real hardware to enable fast modeling of the processor:

  • All memory accesses are performed in programmer view order.
  • Unaligned accesses, where permitted, are always performed as byte transfers.

In addition, some PV models do not use all the transaction states available in a PVBus transaction. The Privileged and Instruction flags are set correctly for ARMv7 processors but might not be set correctly in earlier architectures. However all memory accesses are atomic so SWP instructions behave as expected.

I-side access in PV models

PV models cache translations of instructions fetched from memory-like slaves. The models might not perform further access to those slaves for significant periods. A slave can force the model to reread the memory by declaring that the memory has changed.

PV models do not model a prefetch queue but the code translation mechanism effectively acts as a prefetch queue of variable depth. ARM recommends that you follow the standards in the ARM® Architecture Reference Manual for dealing with prefetch issues, such as self modifying code, and use appropriate cache flushing and synchronization barriers.

Translation of instructions only occurs for memory-like slaves, which are those declared by devices as having type pv::MEMORY. Instructions fetched from device-like slaves are repeatedly fetched, decoded and executed, significantly slowing down model performance.

D-side access in PV models

PV models cache references to the underlying memory of memory-like slaves, and might not perform further accesses to those slaves over the bus for significant periods.

Slaves declared as type pv::MEMORY provide the fastest possible memory access for PV processors.

Slaves declared as type pv::DEVICE are normally used for peripheral access.

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